[PATCH 1/2] clk: st: clkgen-fsyn: search reg within node or parent

[Patrice CHOTARD]

Hi Alain

On 12/2/21 8:28 AM, Alain Volmat wrote:
> In order to avoid having duplicated addresses within the DT,
> only have one unit-address per clockgen and each driver within
> the clockgen should look at the parent node (overall clockgen)
> to figure out the reg property.  Such behavior is already in
> place in other STi platform clock drivers such as clk-flexgen
> and clkgen-pll.  Keep backward compatibility by first looking
> at reg within the node before looking into the parent node.
> 
> Signed-off-by: Alain Volmat <avolmat at me.com>
> ---
>  drivers/clk/st/clkgen-fsyn.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
> index 164285d6be97..0d41164f2c7f 100644
> --- a/drivers/clk/st/clkgen-fsyn.c
> +++ b/drivers/clk/st/clkgen-fsyn.c
> @@ -988,9 +988,16 @@ static void __init st_of_quadfs_setup(struct device_node *np,
>  	void __iomem *reg;
>  	spinlock_t *lock;
>  
> +	/*
> +	 * First check for reg property within the node to keep backward
> +	 * compatibility, then if reg doesn't exist look at the parent node
> +	 */
>  	reg = of_iomap(np, 0);
> -	if (!reg)
> -		return;
> +	if (!reg) {
> +		reg = of_iomap(of_get_parent(np), 0);
> +		if (!reg)
> +			return;
> +	}
>  
>  	clk_parent_name = of_clk_get_parent_name(np, 0);
>  	if (!clk_parent_name)
> 
Reviewed-by: Patrice Chotard <patrice.chotard at foss.st.com>

Thanks
Patrice