[PATCH v2 1/2] perf vendor events: For the Arm Neoverse N2

[John Garry]

On 10/12/2021 12:37, Andrew Kilroy wrote:
> Updates the common and microarch json file to add counters available in
> the Arm Neoverse N2 chip, but should also apply to other ArmV8 and ArmV9
> cpus.  Specified in ArmV8 architecture reference manual
> 
>    https://developer.arm.com/documentation/ddi0487/gb/?lang=en
> 
> Some of the counters added to armv8-common-and-microarch.json are
> specified in the ArmV9 architecture reference manual supplement
> (issue A.a):
> 
>    https://developer.arm.com/documentation/ddi0608/aa
> 
> The additional ArmV9 counters are
> 
>    TRB_WRAP
>    TRCEXTOUT0
>    TRCEXTOUT1
>    TRCEXTOUT2
>    TRCEXTOUT3
>    CTI_TRIGOUT4
>    CTI_TRIGOUT5
>    CTI_TRIGOUT6
>    CTI_TRIGOUT7
> 
> This patch also adds files in pmu-events/arch/arm64/arm/neoverse-n2 for
> perf list to output the counter names in categories.
> 
> Counters on the Neoverse N2 are stated in its reference manual:
> 
>    https://developer.arm.com/documentation/102099/0000
> 
> Signed-off-by: Andrew Kilroy<andrew.kilroy at arm.com>
> ---
>   .../arch/arm64/arm/neoverse-n2/branch.json    |   8 +
>   .../arch/arm64/arm/neoverse-n2/bus.json       |  20 ++
>   .../arch/arm64/arm/neoverse-n2/cache.json     | 155 ++++++++++++++
>   .../arch/arm64/arm/neoverse-n2/exception.json |  47 +++++
>   .../arm64/arm/neoverse-n2/instruction.json    | 143 +++++++++++++
>   .../arch/arm64/arm/neoverse-n2/memory.json    |  38 ++++
>   .../arch/arm64/arm/neoverse-n2/other.json     |   5 +
>   .../arch/arm64/arm/neoverse-n2/pipeline.json  |  23 ++
>   .../arch/arm64/arm/neoverse-n2/spe.json       |  14 ++
>   .../arch/arm64/arm/neoverse-n2/trace.json     |  29 +++
>   .../arm64/armv8-common-and-microarch.json     | 198 ++++++++++++++++++
>   tools/perf/pmu-events/arch/arm64/mapfile.csv  |   1 +
>   12 files changed, 681 insertions(+)
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/other.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/pipeline.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/spe.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/trace.json
> 
> diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/branch.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/branch.json

This looks ok,

Reviewed-by: John Garry <john.garry at huawei.com>

BTW, I was looking at adding perf tool --topdown support for arm64. This 
will require L1 metricgroup support per core - see what I did here for 
our hisilicon platform already:

[0] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/metrics.json

I would like to add support for more cores. Generally the arm common 
events match up to the definitions here:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/Documentation/perf-stat.txt#n400

Apart from frontend_bound - would you have an equivalent metric 
expression for this for these Neoverse cores?

[0] Note that I think that the divisor in the metric expressions is max 
uops that the core can deal with.

Thanks,
John