[PATCH V2] arm64: dts: add support for S4 based Amlogic AQ222

[xianwei.zhao]

On 2021/12/9 下午10:00, Neil Armstrong wrote:
> 
> Hi,
> 
> On 08/12/2021 07:44, xianwei.zhao wrote:
>> Add basic support for the Amlogic S4 based Amlogic AQ222 board:
>> which describe components as follows: CPU, GIC, IRQ, Timer, UART.
>> It's capable of booting up into the serial console.
>>
>> Signed-off-by: xianwei.zhao <xianwei.zhao at amlogic.com>
>> ---
>> V1 -> V2: cleaned up coding style, modify CPU affinity of timer interrups,
>>            and modify GIC reg defintions.
>> ---
>>   arch/arm64/boot/dts/amlogic/Makefile          |  1 +
>>   .../dts/amlogic/meson-s4-s805x2-aq222.dts     | 30 ++++++
>>   arch/arm64/boot/dts/amlogic/meson-s4.dtsi     | 99 +++++++++++++++++++
>>   3 files changed, 130 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
>>   create mode 100644 arch/arm64/boot/dts/amlogic/meson-s4.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
>> index 5148cd9e5146..faea74a45994 100644
>> --- a/arch/arm64/boot/dts/amlogic/Makefile
>> +++ b/arch/arm64/boot/dts/amlogic/Makefile
>> @@ -57,3 +57,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb
>>   dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb
>>   dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb
>>   dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb
>> +dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
>> new file mode 100644
>> index 000000000000..3b340594a125
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
>> @@ -0,0 +1,30 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "meson-s4.dtsi"
>> +
>> +/ {
>> +	model = "Amlogic Meson S4 AQ222 Development Board";
>> +	compatible = "amlogic,aq222";
> 
> According to bindings, it should be: compatible = "amlogic,aq222, "meson,s4"
According to previous patch [0], maybe the following line is reasonable.
compatible = "amlogic,aq222, "amlgoic,s4"

> 
>> +	interrupt-parent = <&gic>;
>> +	#address-cells = <2>;
>> +	#size-cells = <2>;
>> +
>> +	aliases {
>> +		serial0 = &uart_B;
>> +	};
>> +
>> +	memory at 00000000 {
>> +		device_type = "memory";
>> +		reg = <0x0 0x0 0x0 0x40000000>;
>> +	};
>> +
>> +};
>> +
>> +&uart_B {
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
>> new file mode 100644
>> index 000000000000..d7083c93d3d0
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
>> @@ -0,0 +1,99 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> +	cpus:cpus {
>> +		#address-cells = <2>;
>> +		#size-cells = <0>;
>> +
>> +		CPU0:cpu at 0 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a35","arm,armv8";
>> +			reg = <0x0 0x0>;
>> +			enable-method = "psci";
>> +		};
>> +
>> +		CPU1:cpu at 1 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a35","arm,armv8";
>> +			reg = <0x0 0x1>;
>> +			enable-method = "psci";
>> +		};
>> +
>> +		CPU2:cpu at 2 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a35","arm,armv8";
>> +			reg = <0x0 0x2>;
>> +			enable-method = "psci";
>> +		};
>> +
>> +		CPU3:cpu at 3 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a35","arm,armv8";
>> +			reg = <0x0 0x3>;
>> +			enable-method = "psci";
>> +		};
>> +	};
>> +
>> +	timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> +	};
>> +
>> +	psci {
>> +		compatible = "arm,psci-1.0";
>> +		method = "smc";
>> +	};
>> +
>> +	xtal: xtal-clk {
>> +		compatible = "fixed-clock";
>> +		clock-frequency = <24000000>;
>> +		clock-output-names = "xtal";
>> +		#clock-cells = <0>;
>> +	};
>> +
>> +	soc {
>> +		compatible = "simple-bus";
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +
>> +		gic: interrupt-controller at fff01000 {
>> +			compatible = "arm,gic-400";
>> +			#interrupt-cells = <3>;
>> +			#address-cells = <0>;
>> +			interrupt-controller;
>> +			reg = <0x0 0xfff01000 0 0x1000>,
>> +			      <0x0 0xfff02000 0 0x2000>,
>> +			      <0x0 0xfff04000 0 0x2000>,
>> +			      <0x0 0xfff06000 0 0x2000>;
>> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> +		};
>> +
>> +		apb4: apb4 at fe000000 {
>> +			compatible = "simple-bus";
>> +			reg = <0x0 0xfe000000 0x0 0x480000>;
>> +			#address-cells = <2>;
>> +			#size-cells = <2>;
>> +			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
>> +
>> +			uart_B: serial at 7a000 {
>> +				compatible = "amlogic,meson-s4-uart",
>> +					     "amlogic,meson-ao-uart";
> 
> When will you send the serial bindings ?

The related patch is on the way.

> 
>> +				reg = <0x0 0x7a000 0x0 0x18>;
>> +				interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
>> +				status = "disabled";
>> +				clocks = <&xtal>, <&xtal>, <&xtal>;
>> +				clock-names = "xtal", "pclk", "baud";
>> +			};
>> +		};
>> +	};
>> +};
>>
>> base-commit: c5468e3c930d4d2937d3a842a85df0f74e95e152
>>
> 
> No need to send a v3 until both bindings have been accepted.
> 
> Neil
> 
> .
> 


Thanks!




Best regards,




xianwei.zhao

[0] 
https://patchwork.kernel.org/project/linux-amlogic/patch/1568276370-54181-5-git-send-email-jianxin.pan@amlogic.com/