[PATCH 3/3] arm64: dts: imx8qxp: add cache info

[Rob Herring]

On Fri, Nov 12, 2021 at 12:27 AM Peng Fan (OSS) <peng.fan at oss.nxp.com> wrote:
>
> From: Peng Fan <peng.fan at nxp.com>
>
> i.MX8QXP A35 Cluster has 32KB Icache, 32KB Dcache and 512KB L2 Cache
>  - Icache is 2-way set associative
>  - Dcache is 4-way set associative
>  - L2cache is 8-way set associative
>  - Line size are 64bytes
>
> Signed-off-by: Peng Fan <peng.fan at nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 28 ++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 617618edf77e..dbec7c106e0b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -58,6 +58,12 @@ A35_0: cpu at 0 {
>                         compatible = "arm,cortex-a35";
>                         reg = <0x0 0x0>;
>                         enable-method = "psci";
> +                       i-cache-size = <0x8000>;
> +                       i-cache-line-size = <64>;
> +                       i-cache-sets = <256>;
> +                       d-cache-size = <0x8000>;
> +                       d-cache-line-size = <64>;
> +                       d-cache-sets = <128>;

Why do you need all this for the L1? Isn't it discoverable with cache
ID registers?

Rob