[PATCH] PCI: mediatek: Delay 100ms to wait power and clock to become stable

[Lorenzo Pieralisi]

On Thu, 4 Nov 2021 14:21:44 +0800, qizhong cheng wrote:
> Described in PCIe CEM specification setctions 2.2 (PERST# Signal) and
> 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
> be delayed 100ms (TPVPERL) for the power and clock to become stable.
> 
> 

Applied to pci/mediatek, thanks!

[1/1] PCI: mediatek: Delay 100ms to wait power and clock to become stable
      https://git.kernel.org/lpieralisi/pci/c/1fa610f217

Thanks,
Lorenzo