[PATCH v5 06/10] clk: Add Sunplus SP7021 clock driver
kernel test robot
lkp at intel.com
Fri Dec 3 08:09:23 PST 2021
Hi Qin,
I love your patch! Perhaps something to improve:
[auto build test WARNING on clk/clk-next]
[also build test WARNING on tip/irq/core linus/master v5.16-rc3 next-20211203]
[cannot apply to pza/reset/next robh/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Qin-Jian/Add-Sunplus-SP7021-SoC-Support/20211203-154345
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: arc-allyesconfig (https://download.01.org/0day-ci/archive/20211203/202112032353.vXXsrZu2-lkp@intel.com/config)
compiler: arceb-elf-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/ebecbb4f178661a7de3c03b73ccd59722c3ee26c
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Qin-Jian/Add-Sunplus-SP7021-SoC-Support/20211203-154345
git checkout ebecbb4f178661a7de3c03b73ccd59722c3ee26c
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arc SHELL=/bin/bash drivers/clk/ drivers/irqchip/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>
All warnings (new ones prefixed by >>):
drivers/clk/clk-sp7021.c: In function 'plltv_fractional_div':
>> drivers/clk/clk-sp7021.c:304:13: warning: variable 'diff_min_sign' set but not used [-Wunused-but-set-variable]
304 | u32 diff_min_sign = 0;
| ^~~~~~~~~~~~~
drivers/clk/clk-sp7021.c: At top level:
>> drivers/clk/clk-sp7021.c:638:13: warning: no previous prototype for 'clk_register_sp_pll' [-Wmissing-prototypes]
638 | struct clk *clk_register_sp_pll(const char *name, const char *parent,
| ^~~~~~~~~~~~~~~~~~~
vim +/diff_min_sign +304 drivers/clk/clk-sp7021.c
298
299 static long plltv_fractional_div(struct sp_pll *clk, unsigned long freq)
300 {
301 u32 m, r;
302 u32 nint, nfra;
303 u32 diff_min_quotient = 210000000, diff_min_remainder = 0;
> 304 u32 diff_min_sign = 0;
305 unsigned long fvco, nf, f, fout = 0;
306 int sdm, ph;
307
308 /* check freq */
309 if (freq < F_MIN) {
310 pr_warn("%s: %s freq:%lu < F_MIN:%lu, round up\n",
311 __func__, clk_hw_get_name(&clk->hw), freq, F_MIN);
312 freq = F_MIN;
313 } else if (freq > F_MAX) {
314 pr_warn("%s: %s freq:%lu > F_MAX:%lu, round down\n",
315 __func__, clk_hw_get_name(&clk->hw), freq, F_MAX);
316 freq = F_MAX;
317 }
318
319 /* DIVR 0~3 */
320 for (r = 0; r <= 3; r++) {
321 fvco = freq << r;
322 if (fvco <= FVCO_MAX)
323 break;
324 }
325 f = F_27M >> r;
326
327 /* PH_SEL 1/0 */
328 for (ph = 1; ph >= 0; ph--) {
329 const u32 *pp = pt[ph];
330 u32 ms = 1;
331
332 /* SDM_MOD 0/1 */
333 for (sdm = 0; sdm <= 1; sdm++) {
334 u32 mod = mods[sdm];
335
336 /* DIVM 1~32 */
337 for (m = ms; m <= 32; m++) {
338 u32 diff_freq;
339 u32 diff_freq_quotient = 0, diff_freq_remainder = 0;
340 u32 diff_freq_sign = 0; /* 0:Positive number, 1:Negative number */
341
342 nf = fvco * m;
343 nint = nf / pp[3];
344
345 if (nint < pp[1])
346 continue;
347 if (nint > pp[1])
348 break;
349
350 nfra = (((nf % pp[3]) * mod * pp[4]) + (F_27M / 2)) / F_27M;
351 if (nfra)
352 diff_freq = (f * (nint + pp[2]) / pp[0]) -
353 (f * (mod - nfra) / mod / pp[4]);
354 else
355 diff_freq = (f * (nint) / pp[0]);
356
357 diff_freq_quotient = diff_freq / m;
358 diff_freq_remainder = ((diff_freq % m) * 1000) / m;
359
360 if (freq > diff_freq_quotient) {
361 diff_freq_quotient = freq - diff_freq_quotient - 1;
362 diff_freq_remainder = 1000 - diff_freq_remainder;
363 diff_freq_sign = 1;
364 } else {
365 diff_freq_quotient = diff_freq_quotient - freq;
366 diff_freq_sign = 0;
367 }
368
369 if (diff_min_quotient > diff_freq_quotient ||
370 (diff_min_quotient == diff_freq_quotient &&
371 diff_min_remainder > diff_freq_remainder)) {
372 /* found a closer freq, save parameters */
373 clk->p[SEL_FRA] = 1;
374 clk->p[SDM_MOD] = sdm;
375 clk->p[PH_SEL] = ph;
376 clk->p[NFRA] = nfra;
377 clk->p[DIVR] = r;
378 clk->p[DIVM] = m;
379
380 fout = diff_freq / m;
381 diff_min_quotient = diff_freq_quotient;
382 diff_min_remainder = diff_freq_remainder;
383 diff_min_sign = diff_freq_sign;
384 }
385 }
386 }
387 }
388
389 if (!fout) {
390 pr_err("%s: %s freq:%lu not found a valid setting\n",
391 __func__, clk_hw_get_name(&clk->hw), freq);
392 return -EINVAL;
393 }
394
395 return fout;
396 }
397
---
0-DAY CI Kernel Test Service, Intel Corporation
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