[xlnx:xlnx_rebase_v5.10 251/1762] drivers/gpu/drm/xlnx/xlnx_scaler.c:866:3: warning: variable 'nr_rds' is uninitialized when used here
kernel test robot
lkp at intel.com
Thu Aug 26 07:23:59 PDT 2021
tree: https://github.com/Xilinx/linux-xlnx xlnx_rebase_v5.10
head: 09a4215f61493584f4410cab3477003e4046dab9
commit: 9c2aaea5d2da626727258703b85f52281b8673bb [251/1762] drm: xlnx: scaler: Adding vpss-scaler driver
config: riscv-randconfig-r022-20210826 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project ea08c4cd1c0869ec5024a8bb3f5cdf06ab03ae83)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# https://github.com/Xilinx/linux-xlnx/commit/9c2aaea5d2da626727258703b85f52281b8673bb
git remote add xlnx https://github.com/Xilinx/linux-xlnx
git fetch --no-tags xlnx xlnx_rebase_v5.10
git checkout 9c2aaea5d2da626727258703b85f52281b8673bb
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/xlnx/xlnx_scaler.c:866:3: warning: variable 'nr_rds' is uninitialized when used here [-Wuninitialized]
nr_rds += nr_rds_clck;
^~~~~~
drivers/gpu/drm/xlnx/xlnx_scaler.c:821:12: note: initialize the variable 'nr_rds' to silence this warning
int nr_rds;
^
= 0
drivers/gpu/drm/xlnx/xlnx_scaler.c:1394:14: warning: variable 'fmt_out' set but not used [-Wunused-but-set-variable]
u32 fmt_in, fmt_out;
^
drivers/gpu/drm/xlnx/xlnx_scaler.c:1394:6: warning: variable 'fmt_in' set but not used [-Wunused-but-set-variable]
u32 fmt_in, fmt_out;
^
3 warnings generated.
vim +/nr_rds +866 drivers/gpu/drm/xlnx/xlnx_scaler.c
800
801 /**
802 * xv_hscaler_calculate_phases - Calculates h-scaler phases
803 * @scaler: Pointer to scaler registers base
804 * @width_in: input width
805 * @width_out: output width
806 * @pixel_rate: pixel rate
807 *
808 */
809 static void
810 xv_hscaler_calculate_phases(struct xilinx_scaler *scaler,
811 u32 width_in, u32 width_out, u32 pixel_rate)
812 {
813 unsigned int loop_width;
814 unsigned int x, s;
815 int offset = 0;
816 int xwrite_pos = 0;
817 bool output_write_en;
818 bool get_new_pix;
819 u64 phaseH;
820 u32 array_idx = 0;
821 int nr_rds;
822 int nr_rds_clck;
823 unsigned int nphases = scaler->max_num_phases;
824 unsigned int nppc = scaler->pix_per_clk;
825 unsigned int shift = XHSC_STEP_PRECISION_SHIFT - ilog2(nphases);
826
827 loop_width = max_t(u32, width_in, width_out);
828 loop_width = ALIGN(loop_width + nppc - 1, nppc);
829
830 for (x = 0; x < loop_width; x++) {
831 nr_rds_clck = 0;
832 for (s = 0; s < nppc; s++) {
833 phaseH = (offset >> shift) & (nphases - 1);
834 get_new_pix = false;
835 output_write_en = false;
836 if ((offset >> XHSC_STEP_PRECISION_SHIFT) != 0) {
837 get_new_pix = true;
838 offset -= (1 << XHSC_STEP_PRECISION_SHIFT);
839 array_idx++;
840 }
841
842 if (((offset >> XHSC_STEP_PRECISION_SHIFT) == 0) &&
843 xwrite_pos < width_out) {
844 offset += pixel_rate;
845 output_write_en = true;
846 xwrite_pos++;
847 }
848
849 scaler->H_phases[x] |= (phaseH <<
850 (s * XHSC_HPHASE_MULTIPLIER));
851 scaler->H_phases[x] |= (array_idx <<
852 (XHSC_HPHASE_SHIFT_BY_6 +
853 (s * XHSC_HPHASE_MULTIPLIER)));
854 if (output_write_en) {
855 scaler->H_phases[x] |=
856 (XV_HSCALER_PHASESH_V_OUTPUT_WR_EN <<
857 (s * XHSC_HPHASE_MULTIPLIER));
858 }
859
860 if (get_new_pix)
861 nr_rds_clck++;
862 }
863 if (array_idx >= nppc)
864 array_idx &= (nppc - 1);
865
> 866 nr_rds += nr_rds_clck;
867 if (nr_rds >= nppc)
868 nr_rds -= nppc;
869 }
870 }
871
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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