[EXT] Re: [PATCH v2 2/4] perf/marvell: CN10k DDR performance monitor support

[John Garry]

On 19/08/2021 12:52, Bharat Bhushan wrote:
>> Is there anything to stop using adding COMPILE_TEST as a dependency?
>> This really helps build coverage testing for other archs
> Just keeping same as other drivers

I think then that may be something which could be improved for other 
drivers.

> 
>>> +	help
>>> +	  Enable perf support for Marvell DDR Performance monitoring
>>> +	  event on CN10K platform.
>>> +
>>>    endmenu
>>> diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile
>>> index 5260b116c7da..ee1126219d8d 100644
>>> --- a/drivers/perf/Makefile
>>> +++ b/drivers/perf/Makefile
>>> @@ -14,3 +14,4 @@ obj-$(CONFIG_THUNDERX2_PMU) += thunderx2_pmu.o
>>>    obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
>>>    obj-$(CONFIG_ARM_SPE_PMU) += arm_spe_pmu.o
>>>    obj-$(CONFIG_ARM_DMC620_PMU) += arm_dmc620_pmu.o
>>> +obj-$(CONFIG_MARVELL_CN10K_DDR_PMU) += marvell_cn10k_ddr_pmu.o
>>> diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c
>> b/drivers/perf/marvell_cn10k_ddr_pmu.c
>>> new file mode 100644
>>> index 000000000000..8f9e3d1fcd8d
>>> --- /dev/null
>>> +++ b/drivers/perf/marvell_cn10k_ddr_pmu.c
>>> @@ -0,0 +1,606 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/* Marvell CN10K DRAM Subsystem (DSS) Performance Monitor Driver
>>> + *
>>> + * Copyright (C) 2021 Marvell.
>>> + */
>>> +

...

>>> +/* Event counter value registers */
>>> +#define DDRC_PERF_CNT_VALUE_BASE		0x8080
>>> +#define DDRC_PERF_CNT_VALUE(n)	(DDRC_PERF_CNT_VALUE_BASE + 8 * (n))
>>> +
>>> +/* Fixed event counter enable/disable register */
>>> +#define DDRC_PERF_CNT_FREERUN_EN	0x80C0
>>> +#define DDRC_PERF_FREERUN_WRITE_EN	0x1
>>> +#define DDRC_PERF_FREERUN_READ_EN	0x2
>>> +
>>> +/* Fixed event counter control register */
>>> +#define DDRC_PERF_CNT_FREERUN_CTRL	0x80C8
>>> +#define DDRC_FREERUN_WRITE_CNT_CLR	0x1
>>> +#define DDRC_FREERUN_READ_CNT_CLR	0x2
>>> +
>>> +/* Fixed event counter value register */
>>> +#define DDRC_PERF_CNT_VALUE_WR_OP	0x80D0
>>> +#define DDRC_PERF_CNT_VALUE_RD_OP	0x80D8
>>> +#define DDRC_PERF_CNT_VALUE_OVERFLOW	BIT_ULL(48)
>>> +#define DDRC_PERF_CNT_MAX_VALUE		GENMASK_ULL(48, 0)
>> I assume all these macros are used...
> Yes, do you see any unused?

I didn't check

> 
>>> +
>>> +struct cn10k_ddr_pmu {
>>> +	struct pmu pmu;

Thanks,
john