[PATCH 15/17] arm64: allwinner: dts: add DTSI file for R329 SoC

[Icenowy Zheng]

于 2021年8月18日 GMT+08:00 下午5:01:39, Maxime Ripard <maxime at cerno.tech> 写到:
>On Mon, Aug 02, 2021 at 02:22:10PM +0800, Icenowy Zheng wrote:
>> Allwinner R329 is a new SoC focused on smart audio devices.
>> 
>> Add a DTSI file for it.
>> 
>> Signed-off-by: Icenowy Zheng <icenowy at sipeed.com>
>> ---
>>  .../arm64/boot/dts/allwinner/sun50i-r329.dtsi | 244 ++++++++++++++++++
>>  1 file changed, 244 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi
>> 
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi
>> new file mode 100644
>> index 000000000000..bfefa2b734b0
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi
>> @@ -0,0 +1,244 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +// Copyright (c) 2021 Sipeed
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/sun50i-r329-ccu.h>
>> +#include <dt-bindings/reset/sun50i-r329-ccu.h>
>> +#include <dt-bindings/clock/sun50i-r329-r-ccu.h>
>> +#include <dt-bindings/reset/sun50i-r329-r-ccu.h>
>> +
>> +/ {
>> +	interrupt-parent = <&gic>;
>> +	#address-cells = <1>;
>> +	#size-cells = <1>;
>> +
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		cpu0: cpu at 0 {
>> +			compatible = "arm,cortex-a53";
>> +			device_type = "cpu";
>> +			reg = <0>;
>> +			enable-method = "psci";
>> +		};
>> +
>> +		cpu1: cpu at 1 {
>> +			compatible = "arm,cortex-a53";
>> +			device_type = "cpu";
>> +			reg = <1>;
>> +			enable-method = "psci";
>> +		};
>> +	};
>> +
>> +	osc24M: osc24M_clk {
>> +		#clock-cells = <0>;
>> +		compatible = "fixed-clock";
>> +		clock-frequency = <24000000>;
>> +		clock-output-names = "osc24M";
>> +	};
>> +
>> +	psci {
>> +		compatible = "arm,psci-0.2";
>> +		method = "smc";
>> +	};
>> +
>> +	timer {
>> +		compatible = "arm,armv8-timer";
>> +		arm,no-tick-in-suspend;
>> +		interrupts = <GIC_PPI 13
>> +			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
>> +			     <GIC_PPI 14
>> +			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
>> +			     <GIC_PPI 11
>> +			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
>> +			     <GIC_PPI 10
>> +			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
>> +	};
>> +
>> +	soc {
>> +		compatible = "simple-bus";
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges;
>> +
>> +		pio: pinctrl at 2000400 {
>> +			compatible = "allwinner,sun50i-r329-pinctrl";
>> +			reg = <0x02000400 0x400>;
>> +			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
>> +			clock-names = "apb", "hosc", "losc";
>> +			gpio-controller;
>> +			#gpio-cells = <3>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <3>;
>> +
>> +			uart0_pb_pins: uart0-pb-pins {
>> +				pins = "PB4", "PB5";
>> +				function = "uart0";
>> +			};
>> +
>> +			mmc0_pf_pins: mmc0-pf-pins {
>> +				pins = "PF0", "PF1", "PF2",
>> +				       "PF3", "PF4", "PF5";
>> +				function = "mmc0";
>> +			};
>> +
>> +			mmc1_clk_pg0: mmc1-clk-pg0 {
>> +				pins = "PG0";
>> +				function = "mmc1_clk";
>> +			};
>
>Argh, of course it was bound to happen :)
>
>Make sure your DT pass validation though, all your mmc1 node names will report errors.
>
>> +
>> +			mmc1_cmd_pg1: mmc1-clk-pg1 {
>
>s/clk/cmd/ ?
>
>> +				pins = "PG1";
>> +				function = "mmc1_cmd";
>> +			};
>> +
>> +			mmc1_d0_pg2: mmc1-clk-pg2 {
>
>s/clk/d0/
>
>> +				pins = "PG2";
>> +				function = "mmc1_d0";
>> +			};
>> +
>> +			mmc1_d1_pg3: mmc1-clk-pg3 {
>
>s/clk/d1/
>
>> +				pins = "PG3";
>> +				function = "mmc1_d1";
>> +			};
>> +
>> +			mmc1_d2_pg4: mmc1-clk-pg4 {
>
>s/clk/d2/
>
>> +				pins = "PG4";
>> +				function = "mmc1_d2";
>> +			};
>> +
>> +			mmc1_d3_pg5: mmc1-clk-pg5 {
>
>s/clk/d3/
>
>> +				pins = "PG5";
>> +				function = "mmc1_d3";
>> +			};
>> +		};
>> +
>> +		ccu: clock at 2001000 {
>> +			compatible = "allwinner,sun50i-r329-ccu";
>> +			reg = <0x02001000 0x1000>;
>> +			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
>> +			clock-names = "hosc", "losc", "iosc";
>
>Do we have a clock tree for the RTC? Is it the same than the H616?

Nope, it's the same with H6 because of external LOSC crystal is
possible. (Although production M2A SoMs has it NC for cost control.)

What's the same between H616 and R329 is linear day storage of the timekeeping
part, not the clock part.

>
>Maxime

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