[PATCH v2 03/18] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain

[Peng Fan]

> GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain
> 
> From: Marek Vasut <marex at denx.de>
> 
> To bring up the MX8MM GPU domain, it is necessary to configure both
> GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without
> this configuration, the system might hang on boot when bringing up the GPU
> power domain. This is sporadically observed on multiple disparate systems.
> 
> Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both
> GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are
> configured when bringing up the GPU domain. This fixes the sporadic hang.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Signed-off-by: Lucas Stach <l.stach at pengutronix.de>

Reviewed-by: Peng Fan <peng.fan at nxp.com>

> ---
>  drivers/soc/imx/gpcv2.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> c7826ce92f0d..2c43e74db0be 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -679,7 +679,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
>  			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
>  		},
> -		.pgc   = BIT(IMX8MM_PGC_GPU2D),
> +		.pgc   = BIT(IMX8MM_PGC_GPU2D) |
> BIT(IMX8MM_PGC_GPU3D),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
> --
> 2.30.2