[PATCH v3 04/13] ARM: dts: sti: update clkgen-pll entries in stih407-clock

[Patrice CHOTARD]

Hi Alain

On 3/31/21 10:42 PM, Alain Volmat wrote:
> The clkgen-pll driver now embed the clock names (assuming the
> right compatible is used). Remove all clock-output-names property
> and update when necessary the compatible.
> 
> Signed-off-by: Alain Volmat <avolmat at me.com>
> ---
>  arch/arm/boot/dts/stih407-clock.dtsi | 16 +++-------------
>  1 file changed, 3 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
> index ecd568777e5f..2603226a6ca8 100644
> --- a/arch/arm/boot/dts/stih407-clock.dtsi
> +++ b/arch/arm/boot/dts/stih407-clock.dtsi
> @@ -36,8 +36,6 @@
>  				compatible = "st,stih407-clkgen-plla9";
>  
>  				clocks = <&clk_sysin>;
> -
> -				clock-output-names = "clockgen-a9-pll-odf";
>  			};
>  		};
>  
> @@ -74,12 +72,9 @@
>  
>  			clk_s_a0_pll: clk-s-a0-pll {
>  				#clock-cells = <1>;
> -				compatible = "st,clkgen-pll0";
> +				compatible = "st,clkgen-pll0-a0";
>  
>  				clocks = <&clk_sysin>;
> -
> -				clock-output-names = "clk-s-a0-pll-ofd-0";
> -				clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
>  			};
>  
>  			clk_s_a0_flexgen: clk-s-a0-flexgen {
> @@ -112,21 +107,16 @@
>  
>  			clk_s_c0_pll0: clk-s-c0-pll0 {
>  				#clock-cells = <1>;
> -				compatible = "st,clkgen-pll0";
> +				compatible = "st,clkgen-pll0-c0";
>  
>  				clocks = <&clk_sysin>;
> -
> -				clock-output-names = "clk-s-c0-pll0-odf-0";
> -				clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
>  			};
>  
>  			clk_s_c0_pll1: clk-s-c0-pll1 {
>  				#clock-cells = <1>;
> -				compatible = "st,clkgen-pll1";
> +				compatible = "st,clkgen-pll1-c0";
>  
>  				clocks = <&clk_sysin>;
> -
> -				clock-output-names = "clk-s-c0-pll1-odf-0";
>  			};
>  
>  			clk_s_c0_flexgen: clk-s-c0-flexgen {
> 
Reviewed-by: Patrice Chotard <patrice.chotard at foss.st.com>

Thanks
Patrice