[PATCH v2 4/7] dt-bindings: soc: mediatek: apusys: Add new document for APU power domain

[Flora Fu]

On Thu, 2021-04-15 at 10:25 -0500, Rob Herring wrote:
> On Thu, Apr 15, 2021 at 01:52:37PM +0800, Flora Fu wrote:
> > Document the bindings for APU power domain on MediaTek SoC.
> > 
> > Signed-off-by: Flora Fu <flora.fu at mediatek.com>
> > ---
> > Note:
> > This patch depends on MT8192 clock[1] patches which haven't yet been accepted.
> > [1] https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210324104110.13383-7-chun-jie.chen@mediatek.com/__;!!CTRNKA9wMg0ARbw!zINTC3jweo4_C2yxqf9kHaxAXhO-k-I_JplIY4OQ390IeSfk5QCR4ojmFz2gPbBV$ 
> > ---
> >  .../soc/mediatek/mediatek,apu-pm.yaml         | 145 ++++++++++++++++++
> >  1 file changed, 145 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
> > new file mode 100644
> > index 000000000000..6ff966920917
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
> > @@ -0,0 +1,145 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/soc/mediatek/mediatek,apu-pm.yaml*__;Iw!!CTRNKA9wMg0ARbw!zINTC3jweo4_C2yxqf9kHaxAXhO-k-I_JplIY4OQ390IeSfk5QCR4ojmF_yHpQUx$ 
> > +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!zINTC3jweo4_C2yxqf9kHaxAXhO-k-I_JplIY4OQ390IeSfk5QCR4ojmFy1L2FzU$ 
> > +
> > +title: Mediatek APU Power Domains
> > +
> > +maintainers:
> > +  - Flora Fu <flora.fu at mediatek.com>
> > +
> > +description: |
> > +  Mediatek AI Process Unit (APU) include support for power domains which can be
> > +  powered up/down by software.
> > +  APU subsys belonging to a power domain should contain a 'power-domains'
> > +  property that is a phandle for apuspm node representing the domain.
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - mediatek,mt8192-apu-pm
> > +      - const: syscon
> > +
> > +  reg:
> > +    description: Address range of the APU power domain controller.
> > +    maxItems: 1
> > +
> > +  '#address-cells':
> > +    const: 1
> > +
> > +  '#size-cells':
> > +    const: 0
> > +
> > +  '#power-domain-cells':
> > +    const: 1
> > +
> > +  vsram-supply:
> > +    description: apu sram regulator supply.
> > +
> > +  mediatek,scpsys:
> > +    $ref: /schemas/types.yaml#/definitions/phandle
> > +    description: |
> > +      phandle to the device containing the scpsys register range.
> > +
> > +  mediatek,apu-conn:
> > +    $ref: /schemas/types.yaml#/definitions/phandle
> > +    description: |
> > +      phandle to the device containing the scpsys apu conn register range.
> > +
> > +  mediatek,apu-conn1:
> > +    $ref: /schemas/types.yaml#/definitions/phandle
> > +    description: |
> > +      phandle to the device containing the scpsys apu conn1 register range.
> > +
> > +  mediatek,apu-vcore:
> > +    $ref: /schemas/types.yaml#/definitions/phandle
> > +    description: |
> > +      phandle to the device containing the scpsys apu vcore register range.
> > +
> > +patternProperties:
> > +  "^power-domain@[0-9a-f]+$":
> > +    type: object
> > +    description: |
> > +      Represents the power domains within the power controller node as
> > +      documented in Documentation/devicetree/bindings/power/power-domain.yaml.
> > +
> > +    properties:
> > +      reg:
> > +        description: |
> > +          Power domain index. Valid values are defined in:
> > +          "include/dt-bindings/power/mt8182-apu-power.h"
> > +        maxItems: 1
> > +
> > +      '#power-domain-cells':
> > +        description: |
> > +          Must be 0 for nodes representing a single PM domain and 1 for nodes
> > +          providing multiple PM.
> > +
> > +      clocks:
> > +        description: |
> > +          List of phandles of clocks list. Specify by order according to
> > +          power-up sequence.
> > +
> > +      clock-names:
> > +        description: |
> > +          List of names of clocks. Specify by order according to power-up
> > +          sequence.
> > +
> > +      assigned-clocks:
> > +        maxItems: 2
> > +
> > +      assigned-clock-parents:
> > +        maxItems: 2
> > +
> > +      domain-supply:
> > +        description: domain regulator supply.
> > +
> > +    required:
> > +      - reg
> > +      - '#power-domain-cells'
> > +
> > +    additionalProperties: false
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - '#power-domain-cells'
> > +  - vsram-supply
> > +  - mediatek,scpsys
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/mt8192-clk.h>
> > +    apuspm: power-domain at 190f0000 {
> > +        compatible = "mediatek,mt8192-apu-pm", "syscon";
> > +        reg = <0x190f0000 0x1000>;
> > +        #address-cells = <1>;
> > +        #size-cells = <0>;
> > +        #power-domain-cells = <1>;
> 
> So you have domains provided by this node and then...
> 
> > +        vsram-supply = <&mt6359_vsram_md_ldo_reg>;
> > +        mediatek,scpsys = <&scpsys>;
> > +        mediatek,apu-conn = <&apu_conn>;
> > +        mediatek,apu-vcore = <&apu_vcore>;
> > +
> > +        apu_top: power-domain at 0 {
> > +            reg = <0>;
> > +            #power-domain-cells = <0>;
> 
> ...each child node provides a domain. What's the difference?

The hardware @190f0000 have controller for several child power domains
in apu subsys and now only one domain (apu_top) is exposed to mt8192
kernel. For the software extension purpose, the driver parses child
nodes even if it has only one child. In previous v1 patch, I add a
domain id index in a header file but it seems not necessary to create a
standalone file for the case. So I just set the index in the device tree
but keep dts structure to present hardware design.

> 
> > +            clocks = <&topckgen CLK_TOP_DSP_SEL>,
> > +                     <&topckgen CLK_TOP_IPU_IF_SEL>,
> > +                     <&clk26m>,
> > +                     <&topckgen CLK_TOP_UNIVPLL_D6_D2>;
> > +            clock-names = "clk_top_conn",
> > +                          "clk_top_ipu_if",
> > +                          "clk_off",
> > +                          "clk_on_default";
> > +            assigned-clocks = <&topckgen CLK_TOP_DSP_SEL>,
> > +                              <&topckgen CLK_TOP_IPU_IF_SEL>;
> > +            assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
> > +                                     <&topckgen CLK_TOP_UNIVPLL_D6_D2>;
> > +            domain-supply = <&mt6359_vproc1_buck_reg>;
> > +        };
> > +    };
> > -- 
> > 2.18.0
> >