[V2] [PATCH] clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable

[quanyang.wang]

Hi Stephen,

On 4/1/21 9:49 AM, Stephen Boyd wrote:
> Quoting quanyang.wang at windriver.com (2021-03-30 05:17:01)
>> From: Quanyang Wang <quanyang.wang at windriver.com>
>>
>> If there is a IOCTL_SET_PLL_FRAC_MODE request sent to ATF ever,
>> we shouldn't skip invoking PM_CLOCK_ENABLE fn even though this
>> pll has been enabled. In ATF implementation, it will only assign
>> the mode to the variable (struct pm_pll *)pll->mode when handling
>> IOCTL_SET_PLL_FRAC_MODE call. Invoking PM_CLOCK_ENABLE can force
>> ATF send request to PWU to set the pll mode to PLL's register.
>>
>> There is a scenario that happens in enabling VPLL_INT(clk_id:96):
>> 1) VPLL_INT has been enabled during booting.
>> 2) A driver calls clk_set_rate and according to the rate, the VPLL_INT
>>     should be set to FRAC mode. Then zynqmp_pll_set_mode is called
>>     to pass IOCTL_SET_PLL_FRAC_MODE to ATF. Note that at this point
>>     ATF just stores the mode to a variable.
>> 3) This driver calls clk_prepare_enable and zynqmp_pll_enable is
>>     called to try to enable VPLL_INT pll. Because of 1), the function
>>     zynqmp_pll_enable just returns without doing anything after checking
>>     that this pll has been enabled.
>>
>> In the scenario above, the pll mode of VPLL_INT will never be set
>> successfully. So adding set_pll_mode to check condition to fix it.
>>
>> Signed-off-by: Quanyang Wang <quanyang.wang at windriver.com>
>> Tested-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
>> ---
> Any Fixes tag?

Will add it at V3 patch.

Thanks,

Quanyang