[PATCH 07/11] soc: imx: gpcv2: add support for optional resets

[Marek Vasut]

On 9/30/20 6:23 PM, Lucas Stach wrote:
> On Mi, 2020-09-30 at 18:15 +0200, Marek Vasut wrote:
>> On 9/30/20 5:50 PM, Lucas Stach wrote:
>>> Normally the reset for the devices inside the power domain is
>>> triggered automatically from the PGC in the power-up sequencing,
>>> however on i.MX8MM this doesn't work for the GPU power domains.
>>
>> One has to wonder whether the VPU power domain has similar hardware bug
>> on the MX8MM ?
> 
> Nope the VPUs have separate reset bits in the BLK_CTL. So after
> powering up the VPUMIX domain one can assert/deassert reset to the
> individual VPU cores.

Is there any documentation for the BLK_CTL on MX8MM ? I can't find any
in the official RM.

And also, the GPUs need to use SRC reset, does the BLK_CTL reset do the
same "degree" of reset to the VPU as the SRC reset does to the GPUs ?