[PATCH v3 1/4] arm64: dts: ti: k3-j7200: add DMA support

[Suman Anna]

Hi Grygorii,

On 9/18/20 10:38 AM, Grygorii Strashko wrote:
> From: Peter Ujfalusi <peter.ujfalusi at ti.com>
> 
> Add the intr, inta, ringacc and udmap nodes for main and mcu NAVSS.

Need to update the changelog, intr and inta are not part of this revised series.

> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> Signed-off-by: Grygorii Strashko <grygorii.strashko at ti.com>
> Tested-by: Kishon Vijay Abraham I <kishon at ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j7200-main.dtsi     | 36 +++++++++++++++
>  .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 44 +++++++++++++++++++
>  2 files changed, 80 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index 3df49577b06a..c5015df58cd4 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -93,6 +93,42 @@
>  			interrupt-names = "rx_011";
>  			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
>  		};
> +
> +		main_ringacc: ringacc at 3c000000 {
> +			compatible = "ti,am654-navss-ringacc";
> +			reg =	<0x0 0x3c000000 0x0 0x400000>,
> +				<0x0 0x38000000 0x0 0x400000>,
> +				<0x0 0x31120000 0x0 0x100>,
> +				<0x0 0x33000000 0x0 0x40000>;
> +			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
> +			ti,num-rings = <1024>;
> +			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
> +			ti,sci = <&dmsc>;
> +			ti,sci-dev-id = <211>;
> +			msi-parent = <&main_udmass_inta>;
> +		};
> +
> +		main_udmap: dma-controller at 31150000 {
> +			compatible = "ti,j721e-navss-main-udmap";
> +			reg =	<0x0 0x31150000 0x0 0x100>,
> +				<0x0 0x34000000 0x0 0x100000>,
> +				<0x0 0x35000000 0x0 0x100000>;
> +			reg-names = "gcfg", "rchanrt", "tchanrt";
> +			msi-parent = <&main_udmass_inta>;
> +			#dma-cells = <1>;
> +
> +			ti,sci = <&dmsc>;
> +			ti,sci-dev-id = <212>;
> +			ti,ringacc = <&main_ringacc>;
> +
> +			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
> +						<0x0f>, /* TX_HCHAN */
> +						<0x10>; /* TX_UHCHAN */
> +			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
> +						<0x0b>, /* RX_HCHAN */
> +						<0x0c>; /* RX_UHCHAN */
> +			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
> +		};
>  	};
>  
>  	main_pmx0: pinctrl at 11c000 {
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> index ec2745e0768e..7ecdfdb46436 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> @@ -92,4 +92,48 @@
>  		ti,sci-dev-id = <137>;
>  		ti,interrupt-ranges = <16 960 16>;
>  	};
> +
> +	cbass_mcu_navss: navss at 28380000 {
> +		compatible = "simple-mfd";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		dma-coherent;
> +		dma-ranges;
> +		ti,sci-dev-id = <232>;
> +
> +		mcu_ringacc: ringacc at 2b800000 {
> +			compatible = "ti,am654-navss-ringacc";
> +			reg =	<0x0 0x2b800000 0x0 0x400000>,
> +				<0x0 0x2b000000 0x0 0x400000>,
> +				<0x0 0x28590000 0x0 0x100>,
> +				<0x0 0x2a500000 0x0 0x40000>;

Please use style consistent with existing dts nodes, not a fan of mismatched
usage. We are using 0x00 for the higher 32-bit addresses and sizes. Comment
applies to all the nodes and all patches in the series.

regards
Suman

> +			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
> +			ti,num-rings = <286>;
> +			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
> +			ti,sci = <&dmsc>;
> +			ti,sci-dev-id = <235>;
> +			msi-parent = <&main_udmass_inta>;
> +		};
> +
> +		mcu_udmap: dma-controller at 285c0000 {
> +			compatible = "ti,j721e-navss-mcu-udmap";
> +			reg =	<0x0 0x285c0000 0x0 0x100>,
> +				<0x0 0x2a800000 0x0 0x40000>,
> +				<0x0 0x2aa00000 0x0 0x40000>;
> +			reg-names = "gcfg", "rchanrt", "tchanrt";
> +			msi-parent = <&main_udmass_inta>;
> +			#dma-cells = <1>;
> +
> +			ti,sci = <&dmsc>;
> +			ti,sci-dev-id = <236>;
> +			ti,ringacc = <&mcu_ringacc>;
> +
> +			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
> +						<0x0f>; /* TX_HCHAN */
> +			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
> +						<0x0b>; /* RX_HCHAN */
> +			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
> +		};
> +	};
>  };
>