[PATCH 13/19] coresight: etm4x: Clean up exception level masks
Mike Leach
mike.leach at linaro.org
Fri Sep 18 11:35:18 EDT 2020
Hi Suzuki,
On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose <suzuki.poulose at arm.com> wrote:
>
> etm4_get_access_type() calculates the exception level bits
> for use in address comparator registers. This is also used
> by the TRCVICTLR register by shifting to the required position.
>
> This patch cleans up the logic to make etm4_get_access_type()
> calcualte a generic mask which can be used by all users by
Spelling^^
> shifting to their field.
>
> No functional changes, only code cleanups.
>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose at arm.com>
> ---
> .../coresight/coresight-etm4x-sysfs.c | 12 +++---
> drivers/hwtracing/coresight/coresight-etm4x.c | 27 ++++++------
> drivers/hwtracing/coresight/coresight-etm4x.h | 43 ++++++++++++-------
> 3 files changed, 47 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 321ad0dc09b0..b18805694350 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -743,7 +743,7 @@ static ssize_t s_exlevel_vinst_show(struct device *dev,
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> struct etmv4_config *config = &drvdata->config;
>
> - val = (config->vinst_ctrl & ETM_EXLEVEL_S_VICTLR_MASK) >> 16;
> + val = (config->vinst_ctrl & TRCVICTLR_EXLEVEL_S_MASK) >> TRCVICTLR_EXLEVEL_S_SHIFT;
> return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> }
>
> @@ -760,10 +760,10 @@ static ssize_t s_exlevel_vinst_store(struct device *dev,
>
> spin_lock(&drvdata->spinlock);
> /* clear all EXLEVEL_S bits */
> - config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK);
> + config->vinst_ctrl &= ~(TRCVICTLR_EXLEVEL_S_MASK);
> /* enable instruction tracing for corresponding exception level */
> val &= drvdata->s_ex_level;
> - config->vinst_ctrl |= (val << 16);
> + config->vinst_ctrl |= (val << TRCVICTLR_EXLEVEL_S_SHIFT);
> spin_unlock(&drvdata->spinlock);
> return size;
> }
> @@ -778,7 +778,7 @@ static ssize_t ns_exlevel_vinst_show(struct device *dev,
> struct etmv4_config *config = &drvdata->config;
>
> /* EXLEVEL_NS, bits[23:20] */
> - val = (config->vinst_ctrl & ETM_EXLEVEL_NS_VICTLR_MASK) >> 20;
> + val = (config->vinst_ctrl & TRCVICTLR_EXLEVEL_NS_MASK) >> TRCVICTLR_EXLEVEL_NS_SHIFT;
> return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> }
>
> @@ -795,10 +795,10 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev,
>
> spin_lock(&drvdata->spinlock);
> /* clear EXLEVEL_NS bits */
> - config->vinst_ctrl &= ~(ETM_EXLEVEL_NS_VICTLR_MASK);
> + config->vinst_ctrl &= ~(TRCVICTLR_EXLEVEL_NS_MASK);
> /* enable instruction tracing for corresponding exception level */
> val &= drvdata->ns_ex_level;
> - config->vinst_ctrl |= (val << 20);
> + config->vinst_ctrl |= (val << TRCVICTLR_EXLEVEL_NS_SHIFT);
> spin_unlock(&drvdata->spinlock);
> return size;
> }
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index 439e9da41006..53687ec06db9 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -867,20 +867,16 @@ static void etm4_init_arch_data(void *info)
> etm4_cs_lock(drvdata, &csa);
> }
>
> +static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
> +{
> + return etm4_get_access_type(config) << TRCVICTLR_EXLEVEL_SHIFT;
> +}
> +
> /* Set ELx trace filter access in the TRCVICTLR register */
> static void etm4_set_victlr_access(struct etmv4_config *config)
> {
> - u64 access_type;
> -
> - config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK | ETM_EXLEVEL_NS_VICTLR_MASK);
> -
> - /*
> - * TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering
> - * bits in vinst_ctrl, same bit pattern as TRCACATRn values returned by
> - * etm4_get_access_type() but with a relative shift in this register.
> - */
> - access_type = etm4_get_access_type(config) << ETM_EXLEVEL_LSHIFT_TRCVICTLR;
> - config->vinst_ctrl |= (u32)access_type;
> + config->vinst_ctrl &= ~(TRCVICTLR_EXLEVEL_S_MASK | TRCVICTLR_EXLEVEL_NS_MASK);
> + config->vinst_ctrl |= etm4_get_victlr_access_type(config);
> }
>
> static void etm4_set_default_config(struct etmv4_config *config)
> @@ -942,10 +938,15 @@ static u64 etm4_get_access_type(struct etmv4_config *config)
> return access_type;
> }
>
> +static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
> +{
> + return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
> +}
> +
> static void etm4_set_comparator_filter(struct etmv4_config *config,
> u64 start, u64 stop, int comparator)
> {
> - u64 access_type = etm4_get_access_type(config);
> + u64 access_type = etm4_get_comparator_access_type(config);
>
> /* First half of default address comparator */
> config->addr_val[comparator] = start;
> @@ -980,7 +981,7 @@ static void etm4_set_start_stop_filter(struct etmv4_config *config,
> enum etm_addr_type type)
> {
> int shift;
> - u64 access_type = etm4_get_access_type(config);
> + u64 access_type = etm4_get_comparator_access_type(config);
>
> /* Configure the comparator */
> config->addr_val[comparator] = address;
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 407ad6647f36..277c22540db6 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -524,24 +524,35 @@
>
> #define TRCACATR_EXLEVEL_SHIFT 8
#defined twice^^ - this one needs deleting.
>
> -/* secure state access levels - TRCACATRn */
> -#define ETM_EXLEVEL_S_APP BIT(8)
> -#define ETM_EXLEVEL_S_OS BIT(9)
> -#define ETM_EXLEVEL_S_HYP BIT(10)
> -#define ETM_EXLEVEL_S_MON BIT(11)
> -/* non-secure state access levels - TRCACATRn */
> -#define ETM_EXLEVEL_NS_APP BIT(12)
> -#define ETM_EXLEVEL_NS_OS BIT(13)
> -#define ETM_EXLEVEL_NS_HYP BIT(14)
> -#define ETM_EXLEVEL_NS_NA BIT(15)
> -
> -/* access level control in TRCVICTLR - same bits as TRCACATRn but shifted */
> -#define ETM_EXLEVEL_LSHIFT_TRCVICTLR 8
> +/*
> + * Exception level mask for Secure and Non-Secure ELs.
> + * ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn).
> + * The Secure and Non-Secure ELs are always to gether.
> + * Non-secure EL3 is never implemented.
> + */
> +#define ETM_EXLEVEL_S_APP BIT(0)
> +#define ETM_EXLEVEL_S_OS BIT(1)
> +#define ETM_EXLEVEL_S_HYP BIT(2)
> +#define ETM_EXLEVEL_S_MON BIT(3)
> +#define ETM_EXLEVEL_NS_APP BIT(4)
> +#define ETM_EXLEVEL_NS_OS BIT(5)
> +#define ETM_EXLEVEL_NS_HYP BIT(6)
> +
> +#define ETM_EXLEVEL_MASK (GENMASK(6, 0))
> +#define ETM_EXLEVEL_S_MASK (GENMASK(3, 0))
> +#define ETM_EXLEVEL_NS_MASK (GENMASK(6, 4))
> +
> +/* access level controls in TRCACATRn */
> +#define TRCACATR_EXLEVEL_SHIFT 8
> +
> +/* access level control in TRCVICTLR */
> +#define TRCVICTLR_EXLEVEL_SHIFT 16
> +#define TRCVICTLR_EXLEVEL_S_SHIFT 16
> +#define TRCVICTLR_EXLEVEL_NS_SHIFT 20
>
> /* secure / non secure masks - TRCVICTLR, IDR3 */
> -#define ETM_EXLEVEL_S_VICTLR_MASK GENMASK(19, 16)
> -/* NS MON (EL3) mode never implemented */
> -#define ETM_EXLEVEL_NS_VICTLR_MASK GENMASK(22, 20)
> +#define TRCVICTLR_EXLEVEL_S_MASK (ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_S_SHIFT)
> +#define TRCVICTLR_EXLEVEL_NS_MASK (ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_NS_SHIFT)
>
> /*
> * TRCOSLSR.OSM - Bit[3,0]
> --
> 2.24.1
>
Regards
Mike
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
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