[PATCH 10/19] coresight: etm4x: Define DEVARCH register fields

[Mike Leach]

Hi Suzuki,

On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose <suzuki.poulose at arm.com> wrote:
>
> Define the fields of the DEVARCH register for identifying
> a component as an ETMv4.x unit. Going forward, we use the
> DEVARCH register for the component identification, rather
> than the TRCIDR3.
>

TRCIDR1? - but either way, we are not using this for component ID. For
the AMBA path component ID is made using CID + PID + optionally if in
the table UCI - which includes DEVARCH.
TRCIDR1 is simply used to get the architecture version so we can be
sure the driver supports it, and can adjust behaviour for version
dependent elements.

> Cc: Mathieu Poirier <mathieu.poirier at linaro.org>
> Cc: Mike Leach <mike.leach at linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose at arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x.c |  4 ++--
>  drivers/hwtracing/coresight/coresight-etm4x.h | 18 ++++++++++++++++++
>  2 files changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index 40f8113191e0..34b27c26591b 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -1598,8 +1598,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
>  static struct amba_cs_uci_id uci_id_etm4[] = {
>         {
>                 /*  ETMv4 UCI data */
> -               .devarch        = 0x47704a13,
> -               .devarch_mask   = 0xfff0ffff,
> +               .devarch        = ETM_DEVARCH_ETMv4x_ARCH,
> +               .devarch_mask   = ETM_DEVARCH_ID_MASK,
>                 .devtype        = 0x00000013,

Perhaps a good time to change this to a #define constant too.
I assume that if the system access is going to use the coresight
architected registers for ID - it should use the same set as the AMBA
path - i.e. DEVARCH + DEVTYPE.

>         }
>  };
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 4044676d2385..29ffad6a5279 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -497,6 +497,24 @@
>                                          ETM_MODE_EXCL_KERN | \
>                                          ETM_MODE_EXCL_USER)
>
> +#define ETM_DEVARCH_ARCHITECT_MASK             GENMASK(31, 21)
> +#define ETM_DEVARCH_ARCHITECT_ARM              ((0x4 << 28) | (0b0111011 << 21))
> +#define ETM_DEVARCH_PRESENT                    BIT(20)
> +#define ETM_DEVARCH_REVISION_MASK              GENMASK(19, 16)
> +#define ETM_DEVARCH_REVISION_SHIFT             16
> +#define ETM_DEVARCH_ARCHID_MASK                        GENMASK(15, 0)
> +#define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT      12
> +#define ETM_DEVARCH_ARCHID_ARCH_VER(x)         \
> +       (((x) & 0xfUL) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT)
> +#define ETM_DEVARCH_ARCHID_ARCH_PART(x)                ((x) & 0xfffUL)
> +#define ETM_DEVARCH_ARCHID_ETMv4               \
> +       (ETM_DEVARCH_ARCHID_ARCH_VER(4) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13))
> +
> +#define ETM_DEVARCH_ID_MASK                                            \
> +       (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT)
> +#define ETM_DEVARCH_ETMv4x_ARCH                                                \
> +       (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4 | ETM_DEVARCH_PRESENT)
> +
>  #define TRCSTATR_IDLE_BIT              0
>  #define TRCSTATR_PMSTABLE_BIT          1
>  #define ETM_DEFAULT_ADDR_COMP          0
> --
> 2.24.1
>

Regards


Mike
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK