[PATCH v2 28/37] arm64: kasan: Enable TBI EL1

[Catalin Marinas]

On Tue, Sep 15, 2020 at 11:16:10PM +0200, Andrey Konovalov wrote:
> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> index 5ba7ac5e9c77..1687447dee7a 100644
> --- a/arch/arm64/mm/proc.S
> +++ b/arch/arm64/mm/proc.S
> @@ -40,9 +40,13 @@
>  #define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
>  
>  #ifdef CONFIG_KASAN_SW_TAGS
> -#define TCR_KASAN_FLAGS TCR_TBI1
> +#define TCR_KASAN_SW_FLAGS TCR_TBI1
>  #else
> -#define TCR_KASAN_FLAGS 0
> +#define TCR_KASAN_SW_FLAGS 0
> +#endif
> +
> +#ifdef CONFIG_KASAN_HW_TAGS
> +#define TCR_KASAN_HW_FLAGS TCR_TBI1
>  #endif
>  
>  /*
> @@ -462,7 +466,7 @@ SYM_FUNC_START(__cpu_setup)
>  	 */
>  	mov_q	x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
>  			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
> -			TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS
> +			TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS
>  	tcr_clear_errata_bits x10, x9, x5
>  
>  #ifdef CONFIG_ARM64_VA_BITS_52
> @@ -495,6 +499,9 @@ SYM_FUNC_START(__cpu_setup)
>  	/* Update TCR_EL1 if MTE is supported (ID_AA64PFR1_EL1[11:8] > 1) */
>  	cbz	mte_present, 1f
>  	orr	x10, x10, #SYS_TCR_EL1_TCMA1
> +#ifdef CONFIG_KASAN_HW_TAGS
> +	orr	x10, x10, #TCR_KASAN_HW_FLAGS
> +#endif

That's fine in general but see my comment about refactoring the other
patch touching this file, this will move around a bit.

-- 
Catalin