[PATCH v4 4/5] arm64: dts: ti: Add support for J7200 SoC

[Vignesh Raghavendra]

On 9/15/20 5:04 PM, Nishanth Menon wrote:
> On 10:39-20200915, Vignesh Raghavendra wrote:
>> [...]
>>
>> On 9/14/20 9:52 PM, Lokesh Vutla wrote:
>>> +
>>> +	cbass_main: bus at 100000 {
>>> +		compatible = "simple-bus";
>>> +		#address-cells = <2>;
>>> +		#size-cells = <2>;
>>> +		ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
>>> +			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
>>> +			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
>>> +			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
>>> +			 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
>>> +			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
>>> +			 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
>>> +			 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
>>> +
>>> +			 /* MCUSS_WKUP Range */
>>> +			 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
>>> +			 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
>>> +			 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
>>> +			 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
>>> +			 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
>>> +			 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
>>> +			 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
>>> +			 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
>>> +			 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
>>> +			 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
>>> +			 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
>>> +			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
>>> +			 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
>>> +
>>> +		cbass_mcu_wakeup: bus at 28380000 {
>>> +			compatible = "simple-bus";
>>> +			#address-cells = <2>;
>>> +			#size-cells = <2>;
>>> +			ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
>>> +				 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
>>> +				 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
>>> +				 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
>>> +				 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
>>> +				 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
>>> +				 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
>>> +				 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
>>> +				 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
>>> +				 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
>>> +				 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
>>> +				 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
>>> +				 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
>>> +		};
>>> +	};
>>> +};
>>
>> OSPI ranges look good to me... Thanks for adding them!
>>
>> [...]
> 
> Is that a reviewed-by ? if so, please add tag?
>
For OSPI bits:

Reviewed-by: Vignesh Raghavendra <vigneshr at ti.com>