[PATCHv4 2/2] soc: qcom: llcc: Support chipsets that can write to llcc regs

[Sai Prakash Ranjan]

On 2020-09-15 00:16, Stephen Boyd wrote:
> Quoting Sai Prakash Ranjan (2020-09-14 04:13:00)
>> From: "Isaac J. Manjarres" <isaacm at codeaurora.org>
>> 
>> Older chipsets may not be allowed to configure certain LLCC registers
>> as that is handled by the secure side software. However, this is not
>> the case for newer chipsets and they must configure these registers
>> according to the contents of the SCT table, while keeping in mind that
>> older targets may not have these capabilities. So add support to allow
>> such configuration of registers to enable capacity based allocation
>> and power collapse retention for capable chipsets.
>> 
>> Reason for choosing capacity based allocation rather than the default
>> way based allocation is because capacity based allocation allows more
>> finer grain partition and provides more flexibility in configuration.
>> As for the retention through power collapse, it has an advantage where
>> the cache hits are more when we wake up from power collapse although
>> it does burn more power but the exact power numbers are not known at
>> the moment.
>> 
>> Signed-off-by: Isaac J. Manjarres <isaacm at codeaurora.org>
>> Reviewed-by: Douglas Anderson <dianders at chromium.org>
>> (saiprakash.ranjan at codeaurora.org: use existing config and reword 
>> commit msg)
> 
> Should be [ not (
> 

Ok

>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan at codeaurora.org>
>> ---
>>  drivers/soc/qcom/llcc-qcom.c | 27 +++++++++++++++++++++++++--
>>  1 file changed, 25 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/soc/qcom/llcc-qcom.c 
>> b/drivers/soc/qcom/llcc-qcom.c
>> index 60ee31842dea..6aedccff49bb 100644
>> --- a/drivers/soc/qcom/llcc-qcom.c
>> +++ b/drivers/soc/qcom/llcc-qcom.c
>> @@ -375,6 +382,22 @@ static int qcom_llcc_cfg_program(struct 
>> platform_device *pdev)
>>                 if (ret)
>>                         return ret;
>> 
>> +               if (cfg->need_llcc_cfg) {
>> +                       u32 disable_cap_alloc, retain_pc;
>> +
>> +                       disable_cap_alloc = 
>> llcc_table[i].dis_cap_alloc << llcc_table[i].slice_id;
>> +                       ret = regmap_write(drv_data->bcast_regmap,
>> +                                       LLCC_TRP_SCID_DIS_CAP_ALLOC, 
>> disable_cap_alloc);
>> +                       if (ret)
>> +                               return ret;
>> +
>> +                       retain_pc = llcc_table[i].retain_on_pc << 
>> llcc_table[i].slice_id;
>> +                       ret = regmap_write(drv_data->bcast_regmap,
>> +                                       LLCC_TRP_PCB_ACT, retain_pc);
>> +                       if (ret)
>> +                               return ret;
>> +               }
>> +
>>                 if (llcc_table[i].activate_on_init) {
>>                         desc.slice_id = llcc_table[i].slice_id;
>>                         ret = llcc_slice_activate(&desc);
> 
> I thought all of this stuff would move into the config function. So the
> for loop is simplified to a function call and return if failure.

The config function was specifically for attribute config
not for other llcc configs like these, so I will rename
qcom_llcc_attr_cfg() to _qcom_llcc_cfg_program() and move
everything there.

As a side note, I have your mails in my inbox but these
messages are not appearing in the list [1]. For Patch 2,
its on the list [2]. I have noticed same thing on your
messages for previous patches, where your reply for one
patch was on the list but the other one was missing, you
might have to check that.

[1] https://lore.kernel.org/patchwork/patch/1305132/
[2] https://lore.kernel.org/patchwork/patch/1305133/

Same with lore.kernel.org/lkml/ links but since url was big, I gave the
above patchwork links.

Thanks,
Sai

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