[PATCH 3/3] ARM: dts: tacoma: Add data sample phase delay for eMMC
Joel Stanley
joel at jms.id.au
Thu Sep 10 22:03:58 EDT 2020
On Thu, 10 Sep 2020 at 10:55, Andrew Jeffery <andrew at aj.id.au> wrote:
>
> Adjust the phase delay to avoid data timeout splats like the following:
>
> [ 731.368601] mmc0: Timeout waiting for hardware interrupt.
> [ 731.374644] mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
> [ 731.381828] mmc0: sdhci: Sys addr: 0x00000020 | Version: 0x00000002
> [ 731.389012] mmc0: sdhci: Blk size: 0x00007200 | Blk cnt: 0x00000020
> [ 731.396194] mmc0: sdhci: Argument: 0x00462a18 | Trn mode: 0x0000002b
> [ 731.403377] mmc0: sdhci: Present: 0x01f70106 | Host ctl: 0x00000017
> [ 731.410559] mmc0: sdhci: Power: 0x0000000f | Blk gap: 0x00000000
> [ 731.417733] mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x00000107
> [ 731.424915] mmc0: sdhci: Timeout: 0x0000000e | Int stat: 0x00000000
> [ 731.432098] mmc0: sdhci: Int enab: 0x03ff008b | Sig enab: 0x03ff008b
> [ 731.439282] mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000
> [ 731.446464] mmc0: sdhci: Caps: 0x01f80080 | Caps_1: 0x00000007
> [ 731.453647] mmc0: sdhci: Cmd: 0x0000193a | Max curr: 0x001f0f08
> [ 731.460829] mmc0: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0xffffffff
> [ 731.468013] mmc0: sdhci: Resp[2]: 0x320f5913 | Resp[3]: 0x00000900
> [ 731.475195] mmc0: sdhci: Host ctl2: 0x0000008b
> [ 731.480139] mmc0: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0xbe040200
> [ 731.487321] mmc0: sdhci: ============================================
>
> Signed-off-by: Andrew Jeffery <andrew at aj.id.au>
Acked-by: Joel Stanley <joel at jms.id.au>
> ---
> arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
> index 5f4ee67ac787..94ec301ceb73 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
> @@ -179,6 +179,8 @@ &emmc_controller {
>
> &emmc {
> status = "okay";
> + aspeed,input-phase = <0x7>;
> + aspeed,output-phase = <0x1f>;
> };
>
> &fsim0 {
> --
> 2.25.1
>
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