[PATCH v4 10/21] KVM: arm64: Add support for stage-2 page-aging in generic page-table
Will Deacon
will at kernel.org
Thu Sep 10 08:42:04 EDT 2020
On Tue, Sep 08, 2020 at 04:30:15PM +0100, Alexandru Elisei wrote:
> On 9/7/20 4:23 PM, Will Deacon wrote:
> > +kvm_pte_t kvm_pgtable_stage2_mkyoung(struct kvm_pgtable *pgt, u64 addr)
> > +{
> > + kvm_pte_t pte = 0;
> > + stage2_update_leaf_attrs(pgt, addr, 1, KVM_PTE_LEAF_ATTR_LO_S2_AF, 0,
> > + &pte);
> > + dsb(ishst);
>
> I am curious about the DSB above. We don't do it when we clear the AF bit, because
> in the clear_flush_young() mmu notifier, kvm_age_hva() is followed by
> kvm_flush_remote_tlbs() -> kvm_flush_remote_tlbs(), which does a DSB ISHST.
>
> When AF is zero, the entry is not allowed to be stored in a TLB, and that's why we
> don't need to issue a TLBI instruction. Do we do the DSB here to make sure all PEs
> in the inner shareability domain see the updated translation tables? Or there's
> another reason I'm not seeing?
You're right: the DSB is to ensure that the updated PTE is visible to the
page-table walker, as I'm not sure how well we'll handle the spurious access
fault in this case (particularly as is_young() would return true).
Will
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