[PATCH v4 00/21] KVM: arm64: Rewrite page-table code and fault handling

[Gavin Shan]

On 9/10/20 2:06 PM, Gavin Shan wrote:
> Hi Will and Marc,
> 
> On 9/8/20 1:23 AM, Will Deacon wrote:
>> Hi all,
>>
>> Here's version four of the KVM page-table rework I previously posted here:
>>
>>    v1: https://lore.kernel.org/r/20200730153406.25136-1-will@kernel.org
>>    v2: https://lore.kernel.org/r/20200818132818.16065-1-will@kernel.org
>>    v3: https://lore.kernel.org/r/20200825093953.26493-1-will@kernel.org
>>
>> Changes since v3 include:
>>
>>    * Removed some more unused code from the old implementation
>>    * Renumbered KVM_PGTABLE_PROT_* to match file permissions in hex dumps
>>    * Simplified kvm_granule_shift() and removed kvm_start_level()
>>    * Only clear valid bit when invalidating a PTE, leaving phys addr intact
>>    * Fail gracefully when attempting to allocate without a memory cache
>>    * Rewrote stage2_apply_range() as a function instead of a macro
>>    * Fixed fault address rounding with hugetlbfs
>>    * Fixed permission fault handling when dirty logging is enabled
>>    * Added comments
>>    * Added reviewer tags
>>
>> Many thanks to Alex and Gavin for their comments.
>>
>> Will
>>
> 
> [...]
> 
> Eventually, I'm lucky finding a machine from our pool where 16KB page
> size is supported. I tried this series (v4) on this machine, everything
> looks good as we expected:
> 
>     Host:   5.9.0-rc3 + patchset (v4)
>             CONFIG_ARM64_VA_BITS=47
>             CONFIG_ARM64_PAGE_SHIFT=14
>             Hugepagesize: 32768 kB      (from /proc/meminfo)
>     Config: -HugeTLBfs/-THP
>             +HugeTLBfs/-THP
>             -HugeTLBfs/THP
>     Guest:  CONFIG_ARM64_PAGE_SHIFT=12/14/16
> 
> Let me know in case there are more tests needed from my side.
> 

Here is the CPU info retrieved from dmidecode:

Handle 0x0004, DMI type 4, 48 bytes
Processor Information
	Socket Designation: CPU 1
	Type: Central Processor
	Family: ARMv8
	Manufacturer: Ampere(TM)
	ID: 02 00 3F 50 00 00 00 00
	Signature: Implementor 0x50, Variant 0x3, Architecture 15, Part 0x000, Revision 2
	Version: eMAG
	Voltage: 0.9 V
	External Clock: 3000 MHz
	Max Speed: 3300 MHz
	Current Speed: 3000 MHz
	Status: Populated, Enabled
	Upgrade: None
	L1 Cache Handle: 0x0005
	L2 Cache Handle: 0x0006
	L3 Cache Handle: 0x0007
	Serial Number: 000000000000000000D7080502F180DC
	Asset Tag: Not Specified
	Part Number: Not Specified
	Core Count: 32
	Core Enabled: 32
	Thread Count: 32
	Characteristics:
		64-bit capable
		Multi-Core
		Hardware Thread
		Execute Protection
		Enhanced Virtualization

Thanks,
Gavin