[PATCH v5 31/80] drm/vc4: crtc: Clear the PixelValve FIFO during configuration

Maxime Ripard maxime at cerno.tech
Thu Sep 3 04:01:03 EDT 2020

Even though it's not really clear why we need to flush the PV FIFO during
the configuration even though we started by flushing it, experience shows
that without it we get a stale pixel stuck in the FIFO between the HVS and
the PV.

Reviewed-by: Dave Stevenson <dave.stevenson at raspberrypi.com>
Tested-by: Chanwoo Choi <cw00.choi at samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon at samsung.com>
Tested-by: Stefan Wahren <stefan.wahren at i2se.com>
Signed-off-by: Maxime Ripard <maxime at cerno.tech>
 drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 73d918706f7e..00b2c2b011d1 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -358,7 +358,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
 	if (is_dsi)
 		CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 		   vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
 		   VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
git-series 0.9.1

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