[PATCH v3 14/21] KVM: arm64: Add support for stage-2 cache flushing in generic page-table

[Gavin Shan]

Hi Will,

On 8/25/20 7:39 PM, Will Deacon wrote:
> From: Quentin Perret <qperret at google.com>
> 
> Add support for cache flushing a range of the stage-2 address space to
> the generic page-table code.
> 
> Cc: Marc Zyngier <maz at kernel.org>
> Signed-off-by: Quentin Perret <qperret at google.com>
> Signed-off-by: Will Deacon <will at kernel.org>
> ---

Reviewed-by: Gavin Shan <gshan at redhat.com>

>   arch/arm64/include/asm/kvm_pgtable.h | 12 ++++++++++++
>   arch/arm64/kvm/hyp/pgtable.c         | 26 ++++++++++++++++++++++++++
>   2 files changed, 38 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h
> index 0c96b78d791d..ea823fe31913 100644
> --- a/arch/arm64/include/asm/kvm_pgtable.h
> +++ b/arch/arm64/include/asm/kvm_pgtable.h
> @@ -226,6 +226,18 @@ kvm_pte_t kvm_pgtable_stage2_mkold(struct kvm_pgtable *pgt, u64 addr);
>    */
>   bool kvm_pgtable_stage2_is_young(struct kvm_pgtable *pgt, u64 addr);
>   
> +/**
> + * kvm_pgtable_stage2_flush_range() - Clean and invalidate data cache to Point
> + * 				      of Coherency for guest stage-2 address
> + *				      range.
> + * @pgt:	Page-table structure initialised by kvm_pgtable_stage2_init().
> + * @addr:	Intermediate physical address from which to flush.
> + * @size:	Size of the range.
> + *
> + * Return: 0 on success, negative error code on failure.
> + */
> +int kvm_pgtable_stage2_flush(struct kvm_pgtable *pgt, u64 addr, u64 size);
> +
>   /**
>    * kvm_pgtable_walk() - Walk a page-table.
>    * @pgt:	Page-table structure initialised by kvm_pgtable_*_init().
> diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c
> index c218651f8eba..75887185f1e2 100644
> --- a/arch/arm64/kvm/hyp/pgtable.c
> +++ b/arch/arm64/kvm/hyp/pgtable.c
> @@ -762,6 +762,32 @@ bool kvm_pgtable_stage2_is_young(struct kvm_pgtable *pgt, u64 addr)
>   	return pte & KVM_PTE_LEAF_ATTR_LO_S2_AF;
>   }
>   
> +static int stage2_flush_walker(u64 addr, u64 end, u32 level, kvm_pte_t *ptep,
> +			       enum kvm_pgtable_walk_flags flag,
> +			       void * const arg)
> +{
> +	kvm_pte_t pte = *ptep;
> +
> +	if (!kvm_pte_valid(pte) || !stage2_pte_cacheable(pte))
> +		return 0;
> +
> +	stage2_flush_dcache(kvm_pte_follow(pte), kvm_granule_size(level));
> +	return 0;
> +}
> +
> +int kvm_pgtable_stage2_flush(struct kvm_pgtable *pgt, u64 addr, u64 size)
> +{
> +	struct kvm_pgtable_walker walker = {
> +		.cb	= stage2_flush_walker,
> +		.flags	= KVM_PGTABLE_WALK_LEAF,
> +	};
> +
> +	if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
> +		return 0;
> +
> +	return kvm_pgtable_walk(pgt, addr, size, &walker);
> +}
> +
>   int kvm_pgtable_stage2_init(struct kvm_pgtable *pgt, struct kvm *kvm)
>   {
>   	size_t pgd_sz;
> 

Thanks,
Gavin