[linux-sunxi] [PATCH] Disable HS-DDR mode for Olimex A64-OLinuXino variants with eMMC

[Clément Péron]

Hi Philip and Chen-Yu

(+Chen-Yu added as He also have the issue for H5)

On Thu, 22 Oct 2020 at 17:39, Clément Péron <peron.clem at gmail.com> wrote:
>
> Hi Maxime,
>
> On Thu, 22 Oct 2020 at 11:13, Maxime Ripard <maxime at cerno.tech> wrote:
> >
> > Hi,
> >
> > On Thu, Oct 22, 2020 at 09:52:29AM +0200, Clément Péron wrote:
> > > Hi Philipp,
> > >
> > > On Thu, 22 Oct 2020 at 00:10, Philip Rinn <rinni at inventati.org> wrote:
> > > >
> > > > Hi,
> > > >
> > > > the Olimex A64-OLinuXino board comes in various variants, three with eMMC.
> > > > While MMC HS-DDR mode works fine on one of them (A64-OLinuXino-1Ge4GW) it
> > > > doesn't work on the A64-OLinuXino-2Ge8G-IND variant (I don't have the
> > > > third variant so I can't check if it works there).
> > >
> > > We got similar situations for Allwinner H6 (Beelink GS1 and Tanix TX6).
> > >
> > > There is definitely an issue in the MMC sunxi driver with HS-DDR mode
> > > and it's not limited to "olimex,a64-olinuxino-emmc".
> > >
> > > Have a look at this this message posted by Jernej:
> > > https://www.spinics.net/lists/arm-kernel/msg846093.html
> > >
> > > I think we should disable the HS-DDR mode for A64 / H6 like it's done
> > > for H5 and not disable board per board until the issue is resolved.
> >
> > I'm not opposed to that on principle, but "it doesn't work on some
> > board" is not a proper justification to do so. It does on some others,
> > so surely there's more to it and this would just paper over whatever
> > issue we have instead of properly fixing it.
>
> Maybe the term board is not correct, maybe it's the eMMC chip which is
> different.
> I don't know if all Beelink GS1/Tanix TX6 use the same eMMC chip for
> all the boards.
>
> >
> > > If you want to disable only for your board you can set in your
> > > device-tree: mmc-hs200-1_8v; This will switch to HS200 mode without
> > > using the HS-DDR mode.
> >
> > Sigh. Can we at least work on a fix instead of providing terrible
> > workarounds?
>
> I agree with you on this, but my board doesn't have this issue and I
> tried to read the vendor kernel and spot a difference but didn't find
> anything relevant.

After reviewing the correct file this time :P

I catched a slight difference between the mainline and vendor driver
in DDR mode.

the phase is set to 1
case MMC_TIMING_UHS_DDR50:
case MMC_TIMING_MMC_DDR52:
dat_drv_ph = 1;
speed_mod = SM2_HSDDR52_DDR50;
break;

Could you add a hack in DDR mode and see if it's working better ?

Maybe line 738:

#define SDXC_REG_DRV_DL (0x0140)
#define SDXC_DAT_DRV_PH_SEL BIT(17)

rval = mmc_readl(host, REG_DRV_DL);
rval |= SDXC_DAT_DRV_PH_SEL;
mmc_writel(host, REG_DRV_DL, rval);

Regards,
Clement

>
> Regards,
> Clement
>
> >
> > Maxime