[PATCH v2 0/3] Add L1 and L2 error detection for A53 and A57

[Rob Herring]

On Tue, Oct 13, 2020 at 02:50:30PM +0200, Sascha Hauer wrote:
> This driver is based on an earlier version from York Sun which can
> be found here: https://lkml.org/lkml/2018/3/14/1203.
> 
> At that time the conclusion was that this driver is not suitable for
> mainline as it used IMPLEMENTATION DEFINED CPU registers and also
> NXP specific SMC calls. All this was used for the error injection only,
> for error reporting it is not needed.

Have you looked at Amazon's version:
http://lore.kernel.org/r/20200510151310.17372-2-hhhawa@amazon.com

Which is an A57 EDAC driver. Looks like it never got upstream though, 
but it's not clear why.

You'll note that it doesn't have a virtual DT node either.

> This is another try to get this driver to mainline. All error injection
> code has been removed (though it has initially been used to test this
> driver on an i.MX8 SoC), what's left is unfortunately not testable, but
> also doesn't contain none of the doubtful code anymore.
> 
> Changes since v1:
> - Split dt-binding into separate patch
> - Sort local function variables in reverse-xmas tree order
> - drop unnecessary comparison and make variable bool
> 
> Sascha Hauer (2):
>   dt-bindings: edac: Add binding for L1/L2 error detection for Cortex
>     A53/57
>   drivers/edac: Add L1 and L2 error detection for A53 and A57
> 
> York Sun (1):
>   arm64: dts: ls104x: Add L1/L2 cache edac node
> 
>  .../bindings/edac/arm,cortex-a5x-edac.yaml    |  32 +++
>  .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi |   5 +
>  .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi |   5 +
>  drivers/edac/Kconfig                          |   6 +
>  drivers/edac/Makefile                         |   1 +
>  drivers/edac/cortex_arm64_l1_l2.c             | 208 ++++++++++++++++++
>  6 files changed, 257 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml
>  create mode 100644 drivers/edac/cortex_arm64_l1_l2.c
> 
> -- 
> 2.28.0
>