[PATCH 04/11] soc: imx: gpcv2: wait for ADB400 handshake

[Jacky Bai]

> -----Original Message-----
> From: Marek Vasut [mailto:marex at denx.de]
> Sent: Thursday, October 1, 2020 12:23 AM
> To: Lucas Stach <l.stach at pengutronix.de>; Shawn Guo
> <shawnguo at kernel.org>; Rob Herring <robh+dt at kernel.org>
> Cc: devicetree at vger.kernel.org; Frieder Schrempf
> <frieder.schrempf at kontron.de>; patchwork-lst at pengutronix.de; dl-linux-imx
> <linux-imx at nxp.com>; kernel at pengutronix.de; Fabio Estevam
> <festevam at gmail.com>; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 04/11] soc: imx: gpcv2: wait for ADB400 handshake
> 
> On 9/30/20 6:19 PM, Lucas Stach wrote:
> > On Mi, 2020-09-30 at 18:11 +0200, Marek Vasut wrote:
> >> On 9/30/20 5:49 PM, Lucas Stach wrote:
> >>
> >> [...]
> >>
> >>> @@ -176,9 +180,19 @@ static int imx_pgc_power_up(struct
> generic_pm_domain *genpd)
> >>>  			   GPC_PGC_CTRL_PCR, 0);
> >>>
> >>>  	/* request the ADB400 to power up */
> >>> -	if (domain->bits.hsk)
> >>> +	if (domain->bits.hskreq) {
> >>>  		regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
> >>> -				   domain->bits.hsk, domain->bits.hsk);
> >>> +				   domain->bits.hskreq, domain->bits.hskreq);
> >>> +
> >>> +		ret = regmap_read_poll_timeout(domain->regmap,
> GPC_PU_PWRHSK,
> >>> +					       reg_val,
> >>> +					       (reg_val & domain->bits.hskack),
> >>> +					       0, USEC_PER_MSEC);
> >>> +		if (ret) {
> >>> +			dev_err(domain->dev, "failed to power up ADB400\n");
> >>
> >> The ADB400 is a bus bridge, so the bus is being attached here, not
> >> powered up, right ?
> >
> > The bits in the PWRHSK register are called "power down" bits, so I
> > kept this nomenclature. Also I think the ADB400 is mostly isolating
> > the bus in the power domains from the rest of the NoC, "attaching" of
> > the bus is really disabling the isolation.
> >
> > As there are multiple valid naming choices I kept the naming from the
> > RM.
> 
> Maybe NXP can finally explain what these bits really do ?

This bit is used to sync the ADB400 bridge to a known status before MIX side power down & isolation.
Detailed info can be find in ARM's ADB400 TRM.

BR
Jacky Bai