[PATCH 00/11] i.MX8MM power domain support

[Jacky Bai]

> -----Original Message-----
> From: Lucas Stach [mailto:l.stach at pengutronix.de]
> Sent: Wednesday, September 30, 2020 11:50 PM
> To: Shawn Guo <shawnguo at kernel.org>; Rob Herring <robh+dt at kernel.org>
> Cc: dl-linux-imx <linux-imx at nxp.com>; Fabio Estevam
> <festevam at gmail.com>; Frieder Schrempf <frieder.schrempf at kontron.de>;
> Marek Vasut <marex at denx.de>; linux-arm-kernel at lists.infradead.org;
> devicetree at vger.kernel.org; kernel at pengutronix.de;
> patchwork-lst at pengutronix.de
> Subject: [PATCH 00/11] i.MX8MM power domain support
> 
> Hi all,
> 
> this adds power domain support for the i.MX8MM to the existing GPCv2 driver.
> It is not complete yet, as it is still missing the VPU and display power domains,
> as those require support for the BLK_CTL regions of the VPUMIX and
> DISPLAYMIX domains. A Linux driver for those regions on the i.MX8MP is
> currently under development and we plan to use this as a template for the
> i.MX8MM when the dust has settled. The changes in this series have been
> made with this in mind, so once the BLK_CTL driver exists it should be a
> matter of hooking things together via DT, with no further changes required on
> the GPCv2 driver side (famous last words).
> 
> Special thanks to Marek Vasut who helped with testing and debugging of early
> versions of this code.
> 

Lucas,

thanks for working on this, but I think current support for 8MM can NOT 100% work due to HW limitation.
Maybe, we need further discussion before moving forward, otherwise, we will meet awkward situation when NXP
doing LTS upgrade. Below are some info shared.

1. The GPU & VPU related power domains need to do special handling due to HW limitation, can refer to the power domain sequence
  In NXP release.
2. another reason that we do power domain control in TF-A in NXP release is that MAIN NOC power domain can only be controlled by
  TF-A, and before MAIN NOC power domain, we need to check other MIXs' power status. If other power domain is controlled by linux side,
  It is not easy to cross world status sync.
3. either 8MM, 8MN, or 8MP, the power domain design is different, I am not sure if it is the good to add hundreds line of code in GPCv2 each time
  a new SOC is added.

BR
Jacky Bai

> Regards,
> Lucas
> 
> Lucas Stach (11):
>   soc: imx: gpcv2: move to more ideomatic error handling in probe
>   soc: imx: gpcv2: move domain mapping to domain driver probe
>   soc: imx: gpcv2: split power up and power down sequence control
>   soc: imx: gpcv2: wait for ADB400 handshake
>   soc: imx: gpcv2: add runtime PM support for power-domains
>   soc: imx: gpcv2: allow domains without power-sequence control
>   soc: imx: gpcv2: add support for optional resets
>   dt-bindings: add defines for i.MX8MM power domains
>   soc: imx: gpcv2: add support for i.MX8MM power domains
>   arm64: dts: imx8mm: add GPC node and power domains
>   arm64: dts: imx8mm: put USB controllers into power-domains
> 
>  .../bindings/power/fsl,imx-gpcv2.yaml         |   8 +
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi     |  59 +++
>  drivers/soc/imx/gpcv2.c                       | 501
> +++++++++++++++---
>  include/dt-bindings/power/imx8mm-power.h      |  22 +
>  4 files changed, 516 insertions(+), 74 deletions(-)  create mode 100644
> include/dt-bindings/power/imx8mm-power.h
> 
> --
> 2.20.1