[PATCH v5 2/4] dt-bindings: mmc: Add uhs-gpio for Keem Bay UHS-1 Support

[muhammad.husaini.zulkifli at intel.com]

From: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli at intel.com>

Add DT bindings of uhs-gpio for Keem Bay SOC UHS Mode Support

Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli at intel.com>
Acked-by: Michal Simek <michal.simek at xilinx.com>
---
 Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
index 58fe9d02a781..320566a673f0 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
@@ -83,7 +83,7 @@ properties:
       - const: intel,keembay-sdhci-5.1-sd       # Intel Keem Bay SD controller
         description:
           For this device it is strongly suggested to include
-          arasan,soc-ctl-syscon.
+          arasan,soc-ctl-syscon and uhs-gpio.
       - const: intel,keembay-sdhci-5.1-sdio     # Intel Keem Bay SDIO controller
         description:
           For this device it is strongly suggested to include
@@ -152,6 +152,11 @@ properties:
     description:
       The MIO bank number in which the command and data lines are configured.
 
+  uhs-gpio:
+    description:
+      The power mux input will be configure using the GPIO provided
+      to generate either 1.8v or 3.3v output.
+
 dependencies:
   clock-output-names: [ '#clock-cells' ]
   '#clock-cells': [ clock-output-names ]
@@ -300,4 +305,5 @@ examples:
           clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
                    <&scmi_clk KEEM_BAY_PSS_SD0>;
           arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
+          uhs-gpio = <&pca0 17 0>;
     };
-- 
2.17.1