[PATCH] coresight: tmc-etr: Fix barrier packet insertion for perf buffer

[Mathieu Poirier]

On Mon, Nov 30, 2020 at 02:36:02PM +0000, Suzuki K Poulose wrote:
> When the ETR is used in perf mode with a larger buffer (configured
> via sysfs or the default size of 1M) than the perf aux buffer size,
> we end up inserting the barrier packet at the wrong offset, while
> moving the offset forward. i.e, instead of the "new moved offset",
> we insert it at the current hardware buffer offset. These packets
> will not be visible as they are never copied and could lead to
> corruption in the trace decoding side, as the decoder is not aware
> that it needs to reset the decoding.
> 
> Fixes: ec13c78d7b45 ("coresight: tmc-etr: Add barrier packets when moving offset forward")
> Reported-by: Al Grant <al.grant at arm.com>
> Tested-by: Mike Leach <mike.leach at arm.com>
> Cc: Mathieu Poirier <mathieu.poirier at linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose at arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-tmc-etr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index a31a4d7ae25e..bf5230e39c5b 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -1552,7 +1552,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
>  
>  	/* Insert barrier packets at the beginning, if there was an overflow */
>  	if (lost)
> -		tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
> +		tmc_etr_buf_insert_barrier_packet(etr_buf, offset);

I have applied this patch.

Thanks,
Mathieu

>  	tmc_etr_sync_perf_buffer(etr_perf, offset, size);
>  
>  	/*
> -- 
> 2.24.1
>