[RESEND PATCH 07/19] arm64: dts: allwinner: A100: Add PMU mode

[André Przywara]

On 10/11/2020 06:31, Frank Lee wrote:

Hi,

> From: Yangtao Li <frank at allwinnertech.com>
> 
> Add the Performance Monitoring Unit (PMU) device tree node to the A100
> .dtsi, which tells DT users which interrupts are triggered by PMU overflow
> events on each core.

Have you tested that the interrupts actually work? For the A64 there
were wrong in the manual, and we realised only later.
"perf stat" works even without interrupts, but "perf record" requires
interrupts, and will return empty-handed if they don't work.
Can you confirm this?

> 
> Signed-off-by: Yangtao Li <frank at allwinnertech.com>

Without being able to test or verify this, the nodes looks correct, so:

Reviewed-by: Andre Przywara <andre.przywara at arm.com>

Cheers,
Andre

> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> index c34ed8045363..01ff53b5a7a8 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> @@ -25,21 +25,21 @@ cpu0: cpu at 0 {
>  			enable-method = "psci";
>  		};
>  
> -		cpu at 1 {
> +		cpu1: cpu at 1 {
>  			compatible = "arm,cortex-a53";
>  			device_type = "cpu";
>  			reg = <0x1>;
>  			enable-method = "psci";
>  		};
>  
> -		cpu at 2 {
> +		cpu2: cpu at 2 {
>  			compatible = "arm,cortex-a53";
>  			device_type = "cpu";
>  			reg = <0x2>;
>  			enable-method = "psci";
>  		};
>  
> -		cpu at 3 {
> +		cpu3: cpu at 3 {
>  			compatible = "arm,cortex-a53";
>  			device_type = "cpu";
>  			reg = <0x3>;
> @@ -47,6 +47,15 @@ cpu at 3 {
>  		};
>  	};
>  
> +	pmu {
> +		compatible = "arm,cortex-a53-pmu";
> +		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> +	};
> +
>  	psci {
>  		compatible = "arm,psci-1.0";
>  		method = "smc";
>