[PATCH v2 6/7] arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0

[Vignesh Raghavendra]

On 11/9/20 10:34 PM, Kishon Vijay Abraham I wrote:
> Add sub-nodes to SERDES0 DT node to represent SERDES0 is connected
> to PCIe and QSGMII (multi-link SERDES).
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
> ---
>  .../dts/ti/k3-j7200-common-proc-board.dts     | 23 +++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> index ef03e7636b66..65a2e5aeb050 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> @@ -8,6 +8,7 @@
>  #include "k3-j7200-som-p0.dtsi"
>  #include <dt-bindings/net/ti-dp83867.h>
>  #include <dt-bindings/mux/ti-serdes.h>
> +#include <dt-bindings/phy/phy.h>
>  
>  / {
>  	chosen {
> @@ -213,3 +214,25 @@
>  	dr_mode = "otg";
>  	maximum-speed = "high-speed";
>  };
> +
> +&serdes_refclk {
> +	clock-frequency = <100000000>;
> +};

Since this is a reference clk from the board, should the entire node be
here instead of in k3-j7200-main.dtsi?

> +
> +&serdes0 {
> +	serdes0_pcie_link: phy at 0 {
> +		reg = <0>;
> +		cdns,num-lanes = <2>;
> +		#phy-cells = <0>;
> +		cdns,phy-type = <PHY_TYPE_PCIE>;
> +		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
> +	};
> +
> +	serdes0_qsgmii_link: phy at 1 {
> +		reg = <2>;
> +		cdns,num-lanes = <1>;
> +		#phy-cells = <0>;
> +		cdns,phy-type = <PHY_TYPE_QSGMII>;
> +		resets = <&serdes_wiz0 3>;
> +	};
> +};
>