[EXT] Re: [PATCH v4 2/2] ARM: imx6plus: enable internal routing of clk_enet_ref where possible
Sven Van Asbroeck
thesven73 at gmail.com
Tue Jun 30 11:23:45 EDT 2020
On Tue, Jun 30, 2020 at 2:36 AM Andy Duan <fugang.duan at nxp.com> wrote:
> Sven, no matter PHY supply 125Mhz clock to pad or not, GPR5 is to select RGMII
> gtx clock source from:
> - 0 Clock from pad
> - 1 Clock from PLL
> Since i.MX6QP can internally supply clock to MAC, we can set GPR5 bit by default.
That's true. But on the sabresd I notice that the PHY's ref_clk output
is from CLK_25M.
The default ref_clk freq for that PHY is 25 MHz, and I don't see anyone change
the default in the devicetree. I also see that a 25 MHz crystal is fitted, which
also suggests 25 Mhz output.
On the imx6, the default ref_clk frequency from ANATOP is 50Mhz. I don't
see anyone change that default in the devicetree either.
So is it possible that, when we switch GPR5 on, the external 25MHz clock
is replaced by the internal 50MHz clock? If so, I'm not sure it'll work...?
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