[PATCH 2/2] arm64: Add workaround for Arm Cortex-A77 erratum 1508412

Marc Zyngier maz at kernel.org
Tue Jun 30 04:15:15 EDT 2020

Hi Rob,

On 2020-06-29 22:33, Rob Herring wrote:
> On Cortex-A77 r0p0 and r1p0, a sequence of a non-cacheable or device 
> load
> and a store exclusive or PAR_EL1 read can cause a deadlock.
> The workaround requires a DMB SY before and after a PAR_EL1 register 
> read
> and the disabling of KVM. KVM must be disabled to prevent the 
> problematic
> sequence in guests' EL1. This workaround also depends on a firmware
> counterpart to enable the h/w to insert DMB SY after load and store
> exclusive instructions. See the errata document SDEN-1152370 v10 [1] 
> for
> more information.

This seems a bit extreme. Given that this CPU is most likely
used in big-little systems, there is still a bunch of CPUs
on which we could reliably execute guests. It is also likely
that people could run trusted guests.

I would suggest printing a big fat warning and taining the
kernel with TAINT_CPU_OUT_OF_SPEC, together with the required
DSBs in the KVM code.


Jazz is not dead. It just smells funny...

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