[PATCH 4/5] mfd: sprd-sc27xx-spi: Fix divide by zero when allocating register offset/mask

[Lee Jones]

On Mon, 29 Jun 2020, Johan Hovold wrote:

> On Mon, Jun 29, 2020 at 01:32:14PM +0100, Lee Jones wrote:
> > Since ddata->irqs[] is already zeroed when allocated by devm_kcalloc() and
> > dividing 0 by anything is still 0, there is no need to re-assign
> > ddata->irqs[i].* values.  Instead, it should be safe to begin at 1.
> > 
> > This fixes the following W=1 warning:
> > 
> >  drivers/mfd/sprd-sc27xx-spi.c:255 sprd_pmic_probe() debug: sval_binop_unsigned: divide by zero
> > 
> > Cc: Orson Zhai <orsonzhai at gmail.com>
> > Cc: Baolin Wang <baolin.wang7 at gmail.com>
> > Cc: Chunyan Zhang <zhang.lyra at gmail.com>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > ---
> >  drivers/mfd/sprd-sc27xx-spi.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/mfd/sprd-sc27xx-spi.c b/drivers/mfd/sprd-sc27xx-spi.c
> > index c305e941e435c..694a7d429ccff 100644
> > --- a/drivers/mfd/sprd-sc27xx-spi.c
> > +++ b/drivers/mfd/sprd-sc27xx-spi.c
> > @@ -251,7 +251,7 @@ static int sprd_pmic_probe(struct spi_device *spi)
> >  		return -ENOMEM;
> >  
> >  	ddata->irq_chip.irqs = ddata->irqs;
> > -	for (i = 0; i < pdata->num_irqs; i++) {
> > +	for (i = 1; i < pdata->num_irqs; i++) {
> >  		ddata->irqs[i].reg_offset = i / pdata->num_irqs;
> >  		ddata->irqs[i].mask = BIT(i % pdata->num_irqs);
> >  	}
> 
> This doesn't look right either.
> 
> First, the loop is never executed if num_irqs is zero.

The point of the patch is that 0 entries are never processed.

However, what I appear to have overlooked is that BIT(0 % x) is not 0,
it's 1.

> Second, the current code looks bogus too as reg_offset is always set to
> zero and mask to BIT(i)...

Heh.  I wonder if/how this was tested.

I'm going to wait to hear from the authors before attempting to fix
this again.

Baolin, Could you please clarify this for us please?

--
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
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