Boot time regression on Xilinx Zynq7000

[Daniel Mack]

Hi,

I'm seeing a regression on a Zynq7000 board between 5.5 and 5.6 and
bisected it down to f5ac896b6a23eb ("clocksource/drivers/cadence-ttc:
Use ttc driver as platform driver"). With the patch in place, I see a 5
second delay in the kernel boot:

[    1.540000] random: fast init done
[    1.690000] random: crng init done
[    2.720000] libphy: mdio: probed

-- boot freezes for about 5 seconds --

[    7.780000] i2c /dev entries driver
[    7.800000] cdns-i2c e0004000.i2c: 100 kHz mmio e0004000 irq 21
[    7.800000] cdns-i2c e0005000.i2c: 100 kHz mmio e0005000 irq 22
[    7.810000] EDAC MC: ECC not enabled
[    7.820000] Xilinx Zynq CpuIdle Driver started
[    7.820000] sdhci: Secure Digital Host Controller Interface driver
[    7.830000] sdhci: Copyright(c) Pierre Ossman
[    7.830000] sdhci-pltfm: SDHCI platform and OF driver helper
[    7.870000] mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc]
using ADMA
[    7.870000] ledtrig-cpu: registered to indicate activity on CPUs
[    7.880000] clocksource: ttc_clocksource: mask: 0xffff max_cycles:
0xffff, max_idle_ns: 537538477 ns
[    7.890000] clocksource: Switched to clocksource ttc_clocksource


Reverting the patch on top of 5.6 solves this issue. I haven't dug any
further yet. Any idea?


Thanks,
Daniel