[PATCH v7 02/11] dt-bindings: clock: imx-lpcg: add support to parse clocks from device tree
Dong Aisheng
dongas86 at gmail.com
Wed Jul 29 04:06:56 EDT 2020
Hi Rob, Stephen, Shawn,
On Wed, Jul 29, 2020 at 4:05 PM Dong Aisheng <aisheng.dong at nxp.com> wrote:
>
> MX8QM and MX8QXP LPCG Clocks are mostly the same except they may reside
> in different subsystems across CPUs and also vary a bit on the availability.
>
> Same as SCU clock, we want to move the clock definition into device tree
> which can fully decouple the dependency of Clock ID definition from device
> tree and make us be able to write a fully generic lpcg clock driver.
>
> And we can also use the existence of clock nodes in device tree to address
> the device and clock availability differences across different SoCs.
>
> Cc: Sascha Hauer <kernel at pengutronix.de>
> Cc: Michael Turquette <mturquette at baylibre.com>
> Cc: devicetree at vger.kernel.org
> Cc: Shawn Guo <shawnguo at kernel.org>
> Cc: Rob Herring <robh at kernel.org>
> Cc: Stephen Boyd <sboyd at kernel.org>
> Signed-off-by: Dong Aisheng <aisheng.dong at nxp.com>
This patch has been reviewed before, however, i removed your tags due
to the legacy binding
file was removed and switched to json schema.
So i updated this patch to json schema accordingly and need your
kindly re-review.
The former reviewed patch is here:
https://patchwork.kernel.org/patch/11439079/
Regards
Aisheng
> ---
> ChangeLog:
> v6->v7:
> * No other changes except converting to json schema based on the former reviewed
> patches due to the lagecy binding file was removed in latests kernel.
> Because the format is different now, i removed the former R-b
> and A-b tags and request a new review.
> See original patch here:
> https://patchwork.kernel.org/patch/11439079/
> v4->v6:
> * no changes
> v3->v4:
> * change bit-offset property to clock-indices
> * use constant macro to define clock indinces
> * drop hw-autogate property which is still not used by drivers
> v2->v3:
> * no changes
> v1->v2:
> * Update example
> * Add power domain property
> ---
> .../bindings/clock/imx8qxp-lpcg.yaml | 79 ++++++++++++++-----
> include/dt-bindings/clock/imx8-lpcg.h | 14 ++++
> 2 files changed, 74 insertions(+), 19 deletions(-)
> create mode 100644 include/dt-bindings/clock/imx8-lpcg.h
>
> diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml
> index 33f3010f48c3..e709e530e17a 100644
> --- a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml
> +++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml
> @@ -21,27 +21,58 @@ description: |
>
> The clock consumer should specify the desired clock by having the clock
> ID in its "clocks" phandle cell. See the full list of clock IDs from:
> - include/dt-bindings/clock/imx8-clock.h
> + include/dt-bindings/clock/imx8-lpcg.h
>
> properties:
> compatible:
> - enum:
> - - fsl,imx8qxp-lpcg-adma
> - - fsl,imx8qxp-lpcg-conn
> - - fsl,imx8qxp-lpcg-dc
> - - fsl,imx8qxp-lpcg-dsp
> - - fsl,imx8qxp-lpcg-gpu
> - - fsl,imx8qxp-lpcg-hsio
> - - fsl,imx8qxp-lpcg-img
> - - fsl,imx8qxp-lpcg-lsio
> - - fsl,imx8qxp-lpcg-vpu
> -
> + oneOf:
> + - const: fsl,imx8qxp-lpcg
> + - items:
> + - enum:
> + - fsl,imx8qm-lpcg
> + - const: fsl,imx8qxp-lpcg
> + - enum:
> + - fsl,imx8qxp-lpcg-adma
> + - fsl,imx8qxp-lpcg-conn
> + - fsl,imx8qxp-lpcg-dc
> + - fsl,imx8qxp-lpcg-dsp
> + - fsl,imx8qxp-lpcg-gpu
> + - fsl,imx8qxp-lpcg-hsio
> + - fsl,imx8qxp-lpcg-img
> + - fsl,imx8qxp-lpcg-lsio
> + - fsl,imx8qxp-lpcg-vpu
> + deprecated: true
> reg:
> maxItems: 1
>
> '#clock-cells':
> const: 1
>
> + clocks:
> + description: |
> + Input parent clocks phandle array for each clock
> + minItems: 1
> + maxItems: 8
> +
> + clock-indices:
> + description: |
> + An integer array indicating the bit offset for each clock.
> + Refer to <include/dt-bindings/clock/imx8-lpcg.h> for the
> + supported LPCG clock indices.
> + minItems: 1
> + maxItems: 8
> +
> + clock-output-names:
> + description: |
> + Shall be the corresponding names of the outputs.
> + NOTE this property must be specified in the same order
> + as the clock-indices property.
> + minItems: 1
> + maxItems: 8
> +
> + power-domains:
> + maxItems: 1
> +
> required:
> - compatible
> - reg
> @@ -51,23 +82,33 @@ additionalProperties: false
>
> examples:
> - |
> - #include <dt-bindings/clock/imx8-clock.h>
> + #include <dt-bindings/clock/imx8-lpcg.h>
> #include <dt-bindings/firmware/imx/rsrc.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> - clock-controller at 5b200000 {
> - compatible = "fsl,imx8qxp-lpcg-conn";
> - reg = <0x5b200000 0xb0000>;
> + sdhc0_lpcg: clock-controller at 5b200000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5b200000 0x10000>;
> #clock-cells = <1>;
> + clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>,
> + <&conn_ipg_clk>,
> + <&conn_axi_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>,
> + <IMX_LPCG_CLK_4>,
> + <IMX_LPCG_CLK_5>;
> + clock-output-names = "sdhc0_lpcg_per_clk",
> + "sdhc0_lpcg_ipg_clk",
> + "sdhc0_lpcg_ahb_clk";
> + power-domains = <&pd IMX_SC_R_SDHC_0>;
> };
>
> mmc at 5b010000 {
> compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
> interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x5b010000 0x10000>;
> - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
> - <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
> - <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
> + clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
> + <&sdhc0_lpcg IMX_LPCG_CLK_0>,
> + <&sdhc0_lpcg IMX_LPCG_CLK_5>;
> clock-names = "ipg", "per", "ahb";
> power-domains = <&pd IMX_SC_R_SDHC_0>;
> };
> diff --git a/include/dt-bindings/clock/imx8-lpcg.h b/include/dt-bindings/clock/imx8-lpcg.h
> new file mode 100644
> index 000000000000..d202715652c3
> --- /dev/null
> +++ b/include/dt-bindings/clock/imx8-lpcg.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019-2020 NXP
> + * Dong Aisheng <aisheng.dong at nxp.com>
> + */
> +
> +#define IMX_LPCG_CLK_0 0
> +#define IMX_LPCG_CLK_1 4
> +#define IMX_LPCG_CLK_2 8
> +#define IMX_LPCG_CLK_3 12
> +#define IMX_LPCG_CLK_4 16
> +#define IMX_LPCG_CLK_5 20
> +#define IMX_LPCG_CLK_6 24
> +#define IMX_LPCG_CLK_7 28
> --
> 2.23.0
>
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