[PATCH 2/4] perf: arm-spe: Add support for ARMv8.3-SPE

[liwei (GF)]

Hi Leo,

On 2020/7/29 14:29, Leo Yan wrote:
> On Fri, Jul 24, 2020 at 05:16:05PM +0800, Wei Li wrote:
>> Armv8.3 extends the SPE by adding:
>> - Alignment field in the Events packet, and filtering on this event
>>   using PMSEVFR_EL1.
>> - Support for the Scalable Vector Extension (SVE).
>>
>> The main additions for SVE are:
>> - Recording the vector length for SVE operations in the Operation Type
>>   packet. It is not possible to filter on vector length.
>> - Incomplete predicate and empty predicate fields in the Events packet,
>>   and filtering on these events using PMSEVFR_EL1.
> 
> This comment description is not relevant with the changes in this
> patch, so could remove them.
> 
>> Add the corresponding decode process of Events packet and Operation Type
>> packet in perf tool.
> 
> This patch is to add the raw dumping for Events packet and Operation Type
> packet.
> 
>> Signed-off-by: Wei Li <liwei391 at huawei.com>
>> ---
>>  .../arm-spe-decoder/arm-spe-pkt-decoder.c     | 69 ++++++++++++++++++-
>>  1 file changed, 67 insertions(+), 2 deletions(-)
>>
>> diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
>> index b94001b756c7..10a3692839de 100644
>> --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
>> +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
>> @@ -347,6 +347,24 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf,
>>  				blen -= ret;
>>  			}
>>  		}
>> +		if (idx > 2) {
>> +			if (payload & 0x800) {
>> +				ret = snprintf(buf, buf_len, " ALIGNMENT");
>> +				buf += ret;
>> +				blen -= ret;
>> +			}
>> +			if (payload & 0x20000) {
>> +				ret = snprintf(buf, buf_len, " SVE-PRED-PARTIAL");
>> +				buf += ret;
>> +				blen -= ret;
>> +			}
>> +			if (payload & 0x40000) {
>> +				ret = snprintf(buf, buf_len, " SVE-PRED-EMPTY");
>> +				buf += ret;
>> +				blen -= ret;
>> +			}
>> +		}
>> +
> 
> Correct.
> 
>>  		if (ret < 0)
>>  			return ret;
>>  		blen -= ret;
>> @@ -354,8 +372,38 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf,
>>  	}
>>  	case ARM_SPE_OP_TYPE:
>>  		switch (idx) {
>> -		case 0:	return snprintf(buf, buf_len, "%s", payload & 0x1 ?
>> -					"COND-SELECT" : "INSN-OTHER");
>> +		case 0:	{
>> +			if (payload & 0x8) {
> 
> Some nitpicks for packet format checking ...
> 
> For SVE operation, the payload partten is: 0b0xxx1xx0.
> 
> So it's good to check the partten like:
> 
>   /* SVE operation subclass is: 0b0xxx1xx0 */
>   if ((payload & 0x8081) == 0x80) {
>      ....
>   }
> 
> If later the packet format is extended, this will not introduce any
> confliction.

Get it, but i think what you are really meaning is:
if ((payload & 0x89) == 0x80) {
	...
}

> 
>> +				size_t blen = buf_len;
>> +
>> +				ret = snprintf(buf, buf_len, "SVE-OTHER");
>> +				buf += ret;
>> +				blen -= ret;
>> +				if (payload & 0x2) {
> 
> Here should express as binary results: " FP" or " INT".

I think this is a style choice, i add these just like the current code where
processing "AT", "EXCL", "AR", "COND" and so on. So should we modify all the corresponding code together?

> 
>> +					ret = snprintf(buf, buf_len, " FP");
>> +					buf += ret;
>> +					blen -= ret;
>> +				}
>> +				if (payload & 0x4) {
>> +					ret = snprintf(buf, buf_len, " PRED");
> 
> Here should express as binary results: " PRED" or " NOT-PRED".

Ditto.

> 
>> +					buf += ret;
>> +					blen -= ret;
>> +				}
>> +				if (payload & 0x70) {
> 
> This is incorrect.  If bits[6:4] is zero, it presents vector length is 32 bits.
>

I am a little confused here.
Refer to the ARM DDI 0487F.b (ID040120), page D10-2830, if bits[6:4] is zero,
it presents vector length is 32 bits indeed.

>> +					ret = snprintf(buf, buf_len, " EVL %d",
>> +						32 << ((payload & 0x70) >> 4));
>> +					buf += ret;
>> +					blen -= ret;
>> +				}
>> +				if (ret < 0)
>> +					return ret;
>> +				blen -= ret;
>> +				return buf_len - blen;
>> +			} else {
> 
> Here we can check with more accurate format as defined in ARMv8 ARM:
> 
>   /* Other operation subclass is: 0b0000000x */
>   if ((payload & 0xfe) == 0x0) {
>      ....
>   }
> 
>> +				return snprintf(buf, buf_len, "%s", payload & 0x1 ?
>> +						"COND-SELECT" : "INSN-OTHER");
>> +			}
>> +		}
>>  		case 1:	{
>>  			size_t blen = buf_len;
>>  
>> @@ -385,6 +433,23 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf,
>>  				ret = snprintf(buf, buf_len, " SIMD-FP");
>>  				buf += ret;
>>  				blen -= ret;
>> +			} else if (payload & 0x8) {
>> +				if (payload & 0x4) {
>> +					ret = snprintf(buf, buf_len, " PRED");
> 
> Here should express as binary results: " PRED" or " NOT-PRED".

Ditto.

>> +					buf += ret;
>> +					blen -= ret;
>> +				}
>> +				if (payload & 0x70) {
> 
> This is incorrect.  If bits[6:4] is zero, it presents vector length is 32 bits.

Refer to the ARM DDI 0487F.b (ID040120), page D10-2832, if bits[6:4] is zero,
it presents vector length is 32 bits indeed.

>> +					ret = snprintf(buf, buf_len, " EVL %d",
>> +						32 << ((payload & 0x70) >> 4));
>> +					buf += ret;
>> +					blen -= ret;
>> +				}
>> +				if (payload & 0x80) {
>> +					ret = snprintf(buf, buf_len, " SG");
> 
> Here should express as binary results: " SG" or " NOT-SG".


Thanks,
Wei