[PATCH v2 16/18] clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs

[Stephen Boyd]

Quoting Claudiu Beznea (2020-07-22 00:38:24)
> Some of the SAMA7G5 PLLs support multiple outputs (e.g. AUDIO PLL).
> For these, split the PLL clock in two: fractional clock and
> divider clock. In case PLLs supports multiple outputs (since these
> outputs are dividers (with different settings) sharing the same
> fractional part), it will register one fractional clock and multiple
> divider clocks (dividers sharing the fractional clock).
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea at microchip.com>
> ---

Applied to clk-next