[PATCH v2 2/3] clk: zynqmp: Use firmware specific divider clock flags

[Amit Sunil Dhamne]

Hi Michael,
Thanks for the review. Will push the Flag conversion to a new function.

Thanks,
Amit

> -----Original Message-----
> From: Michael Tretter <m.tretter at pengutronix.de>
> Sent: Wednesday, July 22, 2020 6:27 AM
> To: Amit Sunil Dhamne <amitsuni at xilinx.com>
> Cc: mturquette at baylibre.com; sboyd at codeaurora.org; sboyd at kernel.org;
> Michal Simek <michals at xilinx.com>; mark.rutland at arm.com; linux-
> clk at vger.kernel.org; Rajan Vaja <RAJANV at xilinx.com>; Jolly Shah
> <JOLLYS at xilinx.com>; Tejas Patel <TEJASP at xilinx.com>; linux-arm-
> kernel at lists.infradead.org; linux-kernel at vger.kernel.org; Rajan Vaja
> <RAJANV at xilinx.com>; Tejas Patel <TEJASP at xilinx.com>
> Subject: Re: [PATCH v2 2/3] clk: zynqmp: Use firmware specific divider clock
> flags
> 
> On Tue, 21 Jul 2020 23:55:31 -0700, Amit Sunil Dhamne wrote:
> > From: Rajan Vaja <rajan.vaja at xilinx.com>
> >
> > Use ZynqMP specific divider clock flags instead of using CCF flags.
> >
> > Signed-off-by: Rajan Vaja <rajan.vaja at xilinx.com>
> > Signed-off-by: Tejas Patel <tejas.patel at xilinx.com>
> > Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne at xilinx.com>
> > ---
> >  drivers/clk/zynqmp/clk-zynqmp.h |  9 +++++++++
> >  drivers/clk/zynqmp/divider.c    | 16 +++++++++++++++-
> >  2 files changed, 24 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/zynqmp/clk-zynqmp.h
> > b/drivers/clk/zynqmp/clk-zynqmp.h index 3cb6149..ec33525 100644
> > --- a/drivers/clk/zynqmp/clk-zynqmp.h
> > +++ b/drivers/clk/zynqmp/clk-zynqmp.h
> > @@ -32,6 +32,15 @@
> >  /* do not gate, ever */
> >  #define ZYNQMP_CLK_IS_CRITICAL         BIT(11)
> >
> > +/* Type Flags for divider clock */
> > +#define ZYNQMP_CLK_DIVIDER_ONE_BASED           BIT(0)
> > +#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO                BIT(1)
> > +#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO          BIT(2)
> > +#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK         BIT(3)
> > +#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST       BIT(4)
> > +#define ZYNQMP_CLK_DIVIDER_READ_ONLY           BIT(5)
> > +#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO         BIT(6)
> > +
> >  enum topology_type {
> >         TYPE_INVALID,
> >         TYPE_MUX,
> > diff --git a/drivers/clk/zynqmp/divider.c
> > b/drivers/clk/zynqmp/divider.c index 3ab57d9..86cb785 100644
> > --- a/drivers/clk/zynqmp/divider.c
> > +++ b/drivers/clk/zynqmp/divider.c
> > @@ -320,7 +320,21 @@ struct clk_hw *zynqmp_clk_register_divider(const
> char *name,
> >         /* struct clk_divider assignments */
> >         div->is_frac = !!((nodes->flag & CLK_FRAC) |
> >                           (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));
> > -       div->flags = nodes->type_flag;
> > +       div->flags = 0;
> > +       div->flags |= (nodes->type_flag &
> ZYNQMP_CLK_DIVIDER_ONE_BASED) ?
> > +                     CLK_DIVIDER_ONE_BASED : 0;
> > +       div->flags |= (nodes->type_flag &
> ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ?
> > +                     CLK_DIVIDER_POWER_OF_TWO : 0;
> > +       div->flags |= (nodes->type_flag &
> ZYNQMP_CLK_DIVIDER_ALLOW_ZERO) ?
> > +                     CLK_DIVIDER_ALLOW_ZERO : 0;
> > +       div->flags |= (nodes->type_flag &
> ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ?
> > +                     CLK_DIVIDER_HIWORD_MASK : 0;
> > +       div->flags |= (nodes->type_flag &
> ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST) ?
> > +                     CLK_DIVIDER_ROUND_CLOSEST : 0;
> > +       div->flags |= (nodes->type_flag &
> ZYNQMP_CLK_DIVIDER_READ_ONLY) ?
> > +                     CLK_DIVIDER_READ_ONLY : 0;
> > +       div->flags |= (nodes->type_flag &
> ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO) ?
> > +                     CLK_DIVIDER_MAX_AT_ZERO : 0;
> 
> Add a helper function for converting the flags.
> 
> Michael
> 
> >         div->hw.init = &init;
> >         div->clk_id = clk_id;
> >         div->div_type = nodes->type;
> > --
> > 2.7.4
> >
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