[PATCH v8 01/15] PCI: cadence: Use "dma-ranges" instead of "cdns,no-bar-match-nbits" property

[Rob Herring]

On Wed, Jul 22, 2020 at 5:03 AM Kishon Vijay Abraham I <kishon at ti.com> wrote:
>
> Cadence PCIe core driver (host mode) uses "cdns,no-bar-match-nbits"
> property to configure the number of bits passed through from PCIe
> address to internal address in Inbound Address Translation register.
> This only used the NO MATCH BAR.
>
> However standard PCI dt-binding already defines "dma-ranges" to
> describe the address ranges accessible by PCIe controller. Add support
> in Cadence PCIe host driver to parse dma-ranges and configure the
> inbound regions for BAR0, BAR1 and NO MATCH BAR. Cadence IP specifies
> maximum size for BAR0 as 256GB, maximum size for BAR1 as 2 GB.
>
> This adds support to take the next biggest region in "dma-ranges" and
> find the smallest BAR that each of the regions fit in and if there is
> no BAR big enough to hold the region, split the region to see if it can
> be fitted using multiple BARs.
>
> "dma-ranges" of J721E will be
> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
> Since there is no BAR which can hold 2^48 size, NO_MATCH_BAR will be
> used here.
>
> Legacy device tree binding compatibility is maintained by retaining
> support for "cdns,no-bar-match-nbits".
>
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
> ---
> Changes from [1]
> 1) Use list_sort() for sorting the address ranges by size
> 2) Clear CDNS_PCIE_LM_RC_BAR_CFG register before configuring them
>
> [1] -> http://lore.kernel.org/r/20200521080153.5902-1-kishon@ti.com
>  .../controller/cadence/pcie-cadence-host.c    | 251 +++++++++++++++++-
>  drivers/pci/controller/cadence/pcie-cadence.h |  28 +-
>  2 files changed, 262 insertions(+), 17 deletions(-)

Reviewed-by: Rob Herring <robh at kernel.org>