[PATCH 2/2] i2c: cadence: Clear HOLD bit at correct time in Rx path

[Wolfram Sang]

On Fri, Jul 03, 2020 at 07:26:12PM +0530, Raviteja Narayanam wrote:
> There are few issues on Zynq SOC observed in the stress tests causing
> timeout errors. Even though all the data is received, timeout error
> is thrown. This is due to an IP bug in which the COMP bit in ISR is
> not set at end of transfer and completion interrupt is not generated.
> 
> This bug is seen on Zynq platforms when the following condition occurs:
> Master read & HOLD bit set & Transfer size register reaches '0'.
> 
> One workaround is to clear the HOLD bit before the transfer size
> register reaches '0'. The current implementation checks for this at
> the start of the loop and also only for less than FIFO DEPTH case
> (ignoring the equal to case).
> 
> So clear the HOLD bit when the data yet to receive is less than or
> equal to the FIFO DEPTH. This avoids the IP bug condition.
> 
> Signed-off-by: Raviteja Narayanam <raviteja.narayanam at xilinx.com>

Applied to for-current, thanks!

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