[PATCH 3/3] soc: mediatek: pwrap: add pwrap driver for MT6873/8192 SoCs
Matthias Brugger
matthias.bgg at gmail.com
Tue Jul 21 18:51:10 EDT 2020
On 14/07/2020 11:53, Hsin-Hsiung Wang wrote:
> MT6873/8192 are highly integrated SoCs and use PMIC_MT6359 for
> power management. This patch adds pwrap master driver to
> access PMIC_MT6359.
>
> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang at mediatek.com>
> ---
> drivers/soc/mediatek/mtk-pmic-wrap.c | 98 ++++++++++++++++++++++++++++++++----
> 1 file changed, 87 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
> index c897205..6e7f796f 100644
> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> @@ -24,11 +24,13 @@
> #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54
>
> /* macro for wrapper status */
> +#define PWRAP_GET_SWINF_2_FSM(x) (((x) >> 1) & 0x00000007)
> #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)
> #define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)
> #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)
> #define PWRAP_STATE_SYNC_IDLE0 BIT(20)
> #define PWRAP_STATE_INIT_DONE0 BIT(21)
> +#define PWRAP_STATE_INIT_DONE1 BIT(15)
>
> /* macro for WACS FSM */
> #define PWRAP_WACS_FSM_IDLE 0x00
> @@ -74,6 +76,7 @@
> #define PWRAP_CAP_DCM BIT(2)
> #define PWRAP_CAP_INT1_EN BIT(3)
> #define PWRAP_CAP_WDT_SRC1 BIT(4)
> +#define PWRAP_CAP_ARB BIT(5)
This commit should be two patches (at least). One adding PWRAP_CAP_ARB and then
another one adding MT6873 support.
Regards,
Matthias
>
> /* defines for slave device wrapper registers */
> enum dew_regs {
> @@ -348,6 +351,10 @@ enum pwrap_regs {
> PWRAP_ADC_RDATA_ADDR1,
> PWRAP_ADC_RDATA_ADDR2,
>
> + /* MT6873 only regs */
> + PWRAP_SWINF_2_WDATA_31_0,
> + PWRAP_SWINF_2_RDATA_31_0,
> +
> /* MT7622 only regs */
> PWRAP_STA,
> PWRAP_CLR,
> @@ -627,6 +634,17 @@ static int mt6797_regs[] = {
> [PWRAP_DCM_DBC_PRD] = 0x1D4,
> };
>
> +static int mt6873_regs[] = {
> + [PWRAP_INIT_DONE2] = 0x0,
> + [PWRAP_TIMER_EN] = 0x3E0,
> + [PWRAP_INT_EN] = 0x448,
> + [PWRAP_WACS2_CMD] = 0xC80,
> + [PWRAP_SWINF_2_WDATA_31_0] = 0xC84,
> + [PWRAP_SWINF_2_RDATA_31_0] = 0xC94,
> + [PWRAP_WACS2_VLDCLR] = 0xCA4,
> + [PWRAP_WACS2_RDATA] = 0xCA8,
> +};
> +
> static int mt7622_regs[] = {
> [PWRAP_MUX_SEL] = 0x0,
> [PWRAP_WRAP_EN] = 0x4,
> @@ -1045,6 +1063,7 @@ enum pwrap_type {
> PWRAP_MT6765,
> PWRAP_MT6779,
> PWRAP_MT6797,
> + PWRAP_MT6873,
> PWRAP_MT7622,
> PWRAP_MT8135,
> PWRAP_MT8173,
> @@ -1108,16 +1127,30 @@ static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
>
> static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
> {
> - u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
> + u32 val;
> + bool ret;
> +
> + val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
> + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
> + ret = (PWRAP_GET_SWINF_2_FSM(val) == PWRAP_WACS_FSM_IDLE);
> + else
> + ret = (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE);
>
> - return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE;
> + return ret;
> }
>
> static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
> {
> - u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
> + u32 val;
> + bool ret;
> +
> + val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
> + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
> + ret = (PWRAP_GET_SWINF_2_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR);
> + else
> + ret = (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR);
>
> - return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
> + return ret;
> }
>
> /*
> @@ -1172,13 +1205,21 @@ static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
> return ret;
> }
>
> - pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
> + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
> + pwrap_writel(wrp, adr, PWRAP_WACS2_CMD);
> + else
> + pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
>
> ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
> if (ret)
> return ret;
>
> - *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
> + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
> + *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
> + PWRAP_SWINF_2_RDATA_31_0));
> + else
> + *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
> + PWRAP_WACS2_RDATA));
>
> pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
>
> @@ -1228,8 +1269,13 @@ static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
> return ret;
> }
>
> - pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
> - PWRAP_WACS2_CMD);
> + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) {
> + pwrap_writel(wrp, wdata, PWRAP_SWINF_2_WDATA_31_0);
> + pwrap_writel(wrp, BIT(29) | adr, PWRAP_WACS2_CMD);
> + } else {
> + pwrap_writel(wrp, BIT(31) | ((adr >> 1) << 16) | wdata,
> + PWRAP_WACS2_CMD);
> + }
>
> return 0;
> }
> @@ -1485,6 +1531,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
> case PWRAP_MT7622:
> pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
> break;
> + case PWRAP_MT6873:
> case PWRAP_MT8183:
> break;
> }
> @@ -1921,6 +1968,19 @@ static const struct pmic_wrapper_type pwrap_mt6797 = {
> .init_soc_specific = NULL,
> };
>
> +static struct pmic_wrapper_type pwrap_mt6873 = {
> + .regs = mt6873_regs,
> + .type = PWRAP_MT6873,
> + .arb_en_all = 0x777f,
> + .int_en_all = BIT(4) | BIT(5),
> + .int1_en_all = 0,
> + .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
> + .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
> + .caps = PWRAP_CAP_ARB,
> + .init_reg_clock = pwrap_common_init_reg_clock,
> + .init_soc_specific = NULL,
> +};
> +
> static const struct pmic_wrapper_type pwrap_mt7622 = {
> .regs = mt7622_regs,
> .type = PWRAP_MT7622,
> @@ -1999,6 +2059,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
> .compatible = "mediatek,mt6797-pwrap",
> .data = &pwrap_mt6797,
> }, {
> + .compatible = "mediatek,mt6873-pwrap",
> + .data = &pwrap_mt6873,
> + }, {
> .compatible = "mediatek,mt7622-pwrap",
> .data = &pwrap_mt7622,
> }, {
> @@ -2022,6 +2085,7 @@ MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
> static int pwrap_probe(struct platform_device *pdev)
> {
> int ret, irq;
> + u32 rdata;
> struct pmic_wrapper *wrp;
> struct device_node *np = pdev->dev.of_node;
> const struct of_device_id *of_slave_id = NULL;
> @@ -2116,14 +2180,22 @@ static int pwrap_probe(struct platform_device *pdev)
> }
> }
>
> - if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) {
> + if (!HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
> + rdata = pwrap_readl(wrp, PWRAP_WACS2_RDATA) &
> + PWRAP_STATE_INIT_DONE0;
> + else
> + rdata = pwrap_readl(wrp, PWRAP_WACS2_RDATA) &
> + PWRAP_STATE_INIT_DONE1;
> + if (!rdata) {
> dev_dbg(wrp->dev, "initialization isn't finished\n");
> ret = -ENODEV;
> goto err_out2;
> }
>
> /* Initialize watchdog, may not be done by the bootloader */
> - pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
> + if (!(HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)))
> + pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
> +
> /*
> * Since STAUPD was not used on mt8173 platform,
> * so STAUPD of WDT_SRC which should be turned off
> @@ -2132,7 +2204,11 @@ static int pwrap_probe(struct platform_device *pdev)
> if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1))
> pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1);
>
> - pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
> + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
> + pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN);
> + else
> + pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
> +
> pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
> /*
> * We add INT1 interrupt to handle starvation and request exception
>
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