[PATCH v4 1/2] arm64: perf: Add support caps in sysfs

[Will Deacon]

On Tue, Jul 21, 2020 at 03:44:47PM +0800, Shaokun Zhang wrote:
> ARMv8.4-PMU introduces the PMMIR_EL1 registers and some new PMU events,
> like STALL_SLOT etc, are related to it. Let's add a caps directory to
> /sys/bus/event_source/devices/armv8_pmuv3_0/ and support slots from
> PMMIR_EL1 registers in this entry. The user programs can get the slots
> from sysfs directly.
> 
> Cc: Will Deacon <will at kernel.org>
> Cc: Mark Rutland <mark.rutland at arm.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun at hisilicon.com>
> ---
> ChangeLog in v4:
>     * Address Will's comments.
> 
> ChangeLog in v3:
>     * Fix one typo in patch3
> 
> ChangeLog in v2:
>     * Add caps entry in sysfs
>     * Fix the PMU events typos
>     * Add one new patch to correct event ID in sysfs
> 
>  arch/arm64/include/asm/sysreg.h |   2 +
>  arch/arm64/kernel/perf_event.c  | 125 ++++++++++++++++++++++++++++------------
>  include/linux/perf/arm_pmu.h    |   1 +
>  3 files changed, 91 insertions(+), 37 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 463175f80341..56c45a9207c7 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -321,6 +321,8 @@
>  #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
>  #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
>  
> +#define SYS_PMMIR_EL1			sys_reg(3, 0, 9, 14, 6)
> +
>  #define SYS_MAIR_EL1			sys_reg(3, 0, 10, 2, 0)
>  #define SYS_AMAIR_EL1			sys_reg(3, 0, 10, 3, 0)
>  
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index 4d7879484cec..ed0012979271 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -277,6 +277,51 @@ static struct attribute_group armv8_pmuv3_format_attr_group = {
>  	.attrs = armv8_pmuv3_format_attrs,
>  };
>  
> +static int armv8pmu_get_pmu_version(void)
> +{
> +	int pmuver;
> +	u64 dfr0;
> +
> +	dfr0 = read_sysreg(id_aa64dfr0_el1);
> +	pmuver = cpuid_feature_extract_unsigned_field(dfr0,
> +			ID_AA64DFR0_PMUVER_SHIFT);
> +
> +	return pmuver;
> +}
> +
> +static umode_t
> +armv8pmu_caps_attr_is_visible(struct kobject *kobj, struct attribute *attr,
> +			      int unused)
> +{
> +	int pmuver = armv8pmu_get_pmu_version();
> +
> +	if (pmuver >= ID_AA64DFR0_PMUVER_8_4)
> +		return attr->mode;
> +
> +	return 0;
> +}
> +
> +static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
> +			  char *buf)
> +{
> +	int slots = read_sysreg_s(SYS_PMMIR_EL1) & 0xFF;

I'm still worried that this might trigger an UNDEF and panic the kernel
if STALL_SLOTS is not supported. The Arm ARM isn't clear about the
behaviour, so I think we have to assume the worst and check that STALL_SLOTS
is supported as well in armv8pmu_caps_attr_is_visible().

In other words, I think we have to check PMCEID1_EL0 as well as
AA64DFR0_EL1.

Will