[PATCH v3 2/3] arm64: perf: Expose some new events via sysfs

Will Deacon will at kernel.org
Mon Jul 20 06:16:42 EDT 2020


On Thu, Jun 18, 2020 at 09:35:43PM +0800, Shaokun Zhang wrote:
> Some new PMU events can been detected by PMCEID1_EL0, but it can't
> be listed, Let's expose these through sysfs.
> 
> Cc: Will Deacon <will at kernel.org>
> Cc: Mark Rutland <mark.rutland at arm.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun at hisilicon.com>
> ---
>  arch/arm64/include/asm/perf_event.h | 27 +++++++++++++++++++++++++++
>  arch/arm64/kernel/perf_event.c      | 19 +++++++++++++++++++
>  2 files changed, 46 insertions(+)

[...]

> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index 5f2ac87e4b91..32c87cd48cbe 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -222,10 +222,29 @@ static struct attribute *armv8_pmuv3_event_attrs[] = {
>  	ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
>  	ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
>  	ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
> +	ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
> +	ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
> +	ARMV8_EVENT_ATTR(op_SPEC, ARMV8_PMUV3_PERFCTR_OP_SPEC),

Weird capitalisation (op_SPEC) here?

Will



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