ARM64: Question: Supporting outer-no-allocate

[David Clear]

Hi,

I'd like to ask whether we can support the configuration of the TCR and MAIR
registers so as to select outer read-no-allocate, outer write-no-allocate on
ARM memory transactions.  I recognize that this might be quite a limited
use-case so let me explain why I'm asking.

The Pensando ASIC is a PCIE host-attached multi-100Gbps I/O chip that includes
an A72 arm64 complex for internal device management. The hardware data-path
makes extensive use of RAM for in-flight metadata, and performance is
maximized by preventing the ARM from allocating cache lines in L3 that would
evict that metadata, at the acceptable cost of increasing ARM memory latency
through L3.

I'd like to upstream as much support for the chip as possible, but I don't
want to formally post a patch if the idea is objectionable, or if there's
a more acceptable way to accomplish the same goal.

The simplest solution might be a new Kconfig option MMU_OUTER_NO_ALLOCATE
to choose the desired TCR and MAIR values:

arch/arm64/include/asm/sysreg.h:
#ifndef CONFIG_MMU_OUTER_NO_ALLOCATE
#define MAIR_ATTR_NORMAL_WT             UL(0x8b)
#define MAIR_ATTR_NORMAL                UL(0xcf)
#else
#define MAIR_ATTR_NORMAL_WT             UL(0xbb)
#define MAIR_ATTR_NORMAL                UL(0xff)
#endif

arch/arm64/mm/proc.S:
#ifndef CONFIG_MMU_OUTER_NO_ALLOCATE
#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBnWA
#else
#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
#endif

Please let me know if a formal patch based on the above would be
acceptable at all, or if there is a different way to accomplish this.

Regards,
David.