[PATCH v2 3/3] arm64: Add workaround for Arm Cortex-A77 erratum 1508412

[Will Deacon]

On Thu, Jul 02, 2020 at 08:56:05AM -0600, Rob Herring wrote:
> On Thu, Jul 2, 2020 at 5:42 AM Will Deacon <will at kernel.org> wrote:
> >
> > On Wed, Jul 01, 2020 at 03:53:08PM -0600, Rob Herring wrote:
> > > On Cortex-A77 r0p0 and r1p0, a sequence of a non-cacheable or device load
> > > and a store exclusive or PAR_EL1 read can cause a deadlock.
> > >
> > > The workaround requires a DMB SY before and after a PAR_EL1 register read
> > > and the disabling of KVM. KVM must be disabled to prevent the problematic
> > > sequence in guests' EL1. This workaround also depends on a firmware
> > > counterpart to enable the h/w to insert DMB SY after load and store
> > > exclusive instructions. See the errata document SDEN-1152370 v10 [1] for
> > > more information.
> >
> > This ^^ is out of date not that we're not disabling KVM.
> 
> Indeed, I fixed the kconfig text, but missed this.
> 
> > > All the other PAR_EL1 reads besides the one in
> > > is_spurious_el1_translation_fault() are in KVM code, so the work-around is
> > > not needed for them.
> >
> > And I think this now needs some extra work.
> 
> Ugg, that was too easy...
> 
> The KVM code in __translate_far_to_hpfar() has:
> 
> read PAR
> read PAR
> write PAR
> 
> I'm wondering if we need 2 dmbs or 4 here. I'm checking on that.

Also worth checking what happens if the PAR access is executed
speculatively, as in that case we probably can't guarantee that the DMB
instructions are executed at all...

Will