[PATCH] ARM: virt: Relax arch timer version check during early boot

Vladimir Murzin vladimir.murzin at arm.com
Mon Jan 20 03:34:45 PST 2020


Hi Marc,

On 1/20/20 11:14 AM, Marc Zyngier wrote:
> Hi Vladimir,
> 
> On 2020-01-20 11:46, Vladimir Murzin wrote:
>> + Marc
>> + kvmarm at lists.cs.columbia.edu
>>
>> On 1/15/20 2:16 PM, Vladimir Murzin wrote:
>>> Updates to the Generic Timer architecture allow ID_PFR1.GenTimer to
>>> have values other than 0 or 1. At the moment, Linux is quite strict in
>>> the way it handles this field at early boot and will not configure
>>> arch timer if it doesn't find the value 1.
>>>
>>> Since here use ubfx for arch timer version extraction (hyb-stub build
>>> with -march=armv7-a, so it is safe)
>>>
>>> To help backports (even though the code was correct at the time of writing)
>>> Fixes: 8ec58be9f3ff ("ARM: virt: arch_timers: enable access to physical timers")
>>> Signed-off-by: Vladimir Murzin <vladimir.murzin at arm.com>
> 
> I'm not opposed to such a change, but it'd be good to document what other values
> are expected here, as the current (Rev E_a) ARM ARM only mentions values 0 and 1.

That true, ARM ARM doesn't mention it yet. OTOH, should we really care about exact
values as soon it stays compatible?

Cheers
Vladimir

> 
> Thanks,
> 
>         M.
> 
>>> ---
>>>  arch/arm/kernel/hyp-stub.S | 7 +++----
>>>  1 file changed, 3 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
>>> index ae50203..6607fa8 100644
>>> --- a/arch/arm/kernel/hyp-stub.S
>>> +++ b/arch/arm/kernel/hyp-stub.S
>>> @@ -146,10 +146,9 @@ ARM_BE8(orr    r7, r7, #(1 << 25))     @ HSCTLR.EE
>>>  #if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER)
>>>      @ make CNTP_* and CNTPCT accessible from PL1
>>>      mrc    p15, 0, r7, c0, c1, 1    @ ID_PFR1
>>> -    lsr    r7, #16
>>> -    and    r7, #0xf
>>> -    cmp    r7, #1
>>> -    bne    1f
>>> +    ubfx    r7, r7, #16, #4
>>> +    teq    r7, #0
>>> +    beq    1f
>>>      mrc    p15, 4, r7, c14, c1, 0    @ CNTHCTL
>>>      orr    r7, r7, #3        @ PL1PCEN | PL1PCTEN
>>>      mcr    p15, 4, r7, c14, c1, 0    @ CNTHCTL
>>>
> 




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