[PATCH v3 09/16] arm64: mask PAC bits of __builtin_return_address

Catalin Marinas catalin.marinas at arm.com
Fri Jan 17 02:14:32 PST 2020


On Mon, Dec 16, 2019 at 02:17:11PM +0530, Amit Daniel Kachhap wrote:
> diff --git a/arch/arm64/include/asm/compiler.h b/arch/arm64/include/asm/compiler.h
> new file mode 100644
> index 0000000..3cb06f9
> --- /dev/null
> +++ b/arch/arm64/include/asm/compiler.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __ASM_COMPILER_H
> +#define __ASM_COMPILER_H
> +
> +#if defined(CONFIG_ARM64_PTR_AUTH)
> +
> +/*
> + * The EL0/EL1 pointer bits used by a pointer authentication code.
> + * This is dependent on TBI0/TBI1 being enabled, or bits 63:56 would also apply.
> + */
> +#define ptrauth_user_pac_mask()		GENMASK_ULL(54, vabits_actual)

That's the current behaviour but I guess we could extend the mask to 63
here without breaking anything since we don't expect instruction
addresses to be tagged. I also think we should turn TCR_EL1.TBID0 on
when we have PAC present (in a separate patch for both the mask change
and the TCR_EL1 bit as this may be slightly more controversial, a
theoretical ABI change).

> +#define ptrauth_kernel_pac_mask()	(GENMASK_ULL(63, 56) | GENMASK_ULL(54, VA_BITS))

I think the kernel mask should be GENMASK_ULL(63, vabits_actual), no
need to skip bit 55 since it's 1 already.

With regards to VA_BITS (a constant), I'm not sure that's correct.
ARMv8.2-LVA (52-bit VA) is an optional feature and I don't think PAC in
8.3 mandates it.

-- 
Catalin



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